Bit parallel 6T SRAM in-memory computing with reconfigurable bit-precision

Kyeongho Lee; Jinho Jeong; Sungsoo Cheon; Woong Choi; Jongsun Park

doi:10.1109/DAC18072.2020.9218567

Bit parallel 6T SRAM in-memory computing with reconfigurable bit-precision

Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

50 Citations (Scopus)

Abstract

This paper presents 6T SRAM cell-based bit-parallel in-memory computing (IMC) architecture to support various computations with reconfigurable bit-precision. In the proposed technique, bit-line computation is performed with a short WL followed by BL boosting circuits, which can reduce BL computing delays. By per-forming carry-propagation between each near-memory circuit, bit-parallel complex computations are also enabled by iterating operations with low latency. In addition, reconfigurable bit-precision is also supported based on carry-propagation size. Our 128KB in/near memory computing architecture has been implemented using a 28nm CMOS process, and it can achieve 2.25GHz clock frequency at 0.9V with 5.2% of area overhead. The proposed architecture also achieves 0.68, 8.09 TOPS/W for the parallel addition and multiplication, respectively. In addition, the proposed work also supports a wide range of supply voltage, from 0.6V to 1.1V.

Original language	English
Title of host publication	2020 57th ACM/IEEE Design Automation Conference, DAC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781450367257
DOIs	https://doi.org/10.1109/DAC18072.2020.9218567
Publication status	Published - 2020 Jul
Event	57th ACM/IEEE Design Automation Conference, DAC 2020 - Virtual, San Francisco, United States Duration: 2020 Jul 20 → 2020 Jul 24

Publication series

Name	Proceedings - Design Automation Conference
Volume	2020-July
ISSN (Print)	0738-100X

Conference

Conference	57th ACM/IEEE Design Automation Conference, DAC 2020
Country/Territory	United States
City	Virtual, San Francisco
Period	20/7/20 → 20/7/24

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

Bitline Computing
In-Memory Computing
Processing-In-memory
Read Disturb
Short Pulse WL

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modelling and Simulation

Access to Document

10.1109/DAC18072.2020.9218567

Cite this

Lee, K., Jeong, J., Cheon, S., Choi, W., & Park, J. (2020). Bit parallel 6T SRAM in-memory computing with reconfigurable bit-precision. In 2020 57th ACM/IEEE Design Automation Conference, DAC 2020 Article 9218567 (Proceedings - Design Automation Conference; Vol. 2020-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DAC18072.2020.9218567

Bit parallel 6T SRAM in-memory computing with reconfigurable bit-precision. / Lee, Kyeongho; Jeong, Jinho; Cheon, Sungsoo et al.
2020 57th ACM/IEEE Design Automation Conference, DAC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9218567 (Proceedings - Design Automation Conference; Vol. 2020-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, K, Jeong, J, Cheon, S, Choi, W & Park, J 2020, Bit parallel 6T SRAM in-memory computing with reconfigurable bit-precision. in 2020 57th ACM/IEEE Design Automation Conference, DAC 2020., 9218567, Proceedings - Design Automation Conference, vol. 2020-July, Institute of Electrical and Electronics Engineers Inc., 57th ACM/IEEE Design Automation Conference, DAC 2020, Virtual, San Francisco, United States, 20/7/20. https://doi.org/10.1109/DAC18072.2020.9218567

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abstract = "This paper presents 6T SRAM cell-based bit-parallel in-memory computing (IMC) architecture to support various computations with reconfigurable bit-precision. In the proposed technique, bit-line computation is performed with a short WL followed by BL boosting circuits, which can reduce BL computing delays. By per-forming carry-propagation between each near-memory circuit, bit-parallel complex computations are also enabled by iterating operations with low latency. In addition, reconfigurable bit-precision is also supported based on carry-propagation size. Our 128KB in/near memory computing architecture has been implemented using a 28nm CMOS process, and it can achieve 2.25GHz clock frequency at 0.9V with 5.2% of area overhead. The proposed architecture also achieves 0.68, 8.09 TOPS/W for the parallel addition and multiplication, respectively. In addition, the proposed work also supports a wide range of supply voltage, from 0.6V to 1.1V.",

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AB - This paper presents 6T SRAM cell-based bit-parallel in-memory computing (IMC) architecture to support various computations with reconfigurable bit-precision. In the proposed technique, bit-line computation is performed with a short WL followed by BL boosting circuits, which can reduce BL computing delays. By per-forming carry-propagation between each near-memory circuit, bit-parallel complex computations are also enabled by iterating operations with low latency. In addition, reconfigurable bit-precision is also supported based on carry-propagation size. Our 128KB in/near memory computing architecture has been implemented using a 28nm CMOS process, and it can achieve 2.25GHz clock frequency at 0.9V with 5.2% of area overhead. The proposed architecture also achieves 0.68, 8.09 TOPS/W for the parallel addition and multiplication, respectively. In addition, the proposed work also supports a wide range of supply voltage, from 0.6V to 1.1V.

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Bit parallel 6T SRAM in-memory computing with reconfigurable bit-precision

Abstract

Publication series

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Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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