Bit-width reduction and customized register for low cost convolutional neural network accelerator

Kyungrak Choi; Woong Choi; Kyungho Shin; Jongsun Park

doi:10.1109/ISLPED.2017.8009164

Bit-width reduction and customized register for low cost convolutional neural network accelerator

Kyungrak Choi
, Woong Choi
, Kyungho Shin
, Jongsun Park

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

This paper presents a low area and energy efficient hardware accelerator for the deep convolutional neural networks (CNNs). Based on the multiply-accumulate (MAC) based architecture, three design techniques are proposed to reduce the hardware cost of the convolutional computations. First, to reduce the computational bit-width of convolutions, an adaptive bit-width reduction scheme is proposed based on differential input method. The bit-width reduction approach can reduce the 37 % of operation bit-width with almost ignorable CNN accuracy degradation. Second, it has been found that adapting bi-directional filtering window in CNN accelerator can considerably reduce the energy for data movement with much smaller number of memory accesses. To expedite the bi-directional filtering operations, we also propose a bidirectional first-input-first-output (bi-FIFO). With SRAM bit-cell layout manner, the proposed bi-FIFO facilitates fast data re-distribution with area and energy efficiency. To verify the effectiveness of the proposed techniques, the AlexNet accelerator has been designed. The numerical results show that the proposed adaptive bit-width reduction scheme achieves 25.9% and 47.3% of area and energy savings, respectively. The bi-FIFO based accelerator also achieves 33 % improved processing time.

Original language	English
Title of host publication	ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509060238
DOIs	https://doi.org/10.1109/ISLPED.2017.8009164
Publication status	Published - 2017 Aug 11
Event	22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 - Taipei, Taiwan, Province of China Duration: 2017 Jul 24 → 2017 Jul 26

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017
Country/Territory	Taiwan, Province of China
City	Taipei
Period	17/7/24 → 17/7/26

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This work was supported bythe National Research Foundation of Korea grant funded by the Korea government (NRF-2016 R1A2B4015329 and NRF-2015M3D1A1070465), and the Information Technology Research and Development Program of Korea Evaluation Institute of Industrial Technology [10052716, Design technology development of ultralow voltage operating circuit and IP for smart sensor SoC]

Publisher Copyright:
© 2017 IEEE.

Keywords

Convolutional Neural Network
Deep Neural Network
Energy Efficiency
FIFO
Filter
Line Buffer
Weight

ASJC Scopus subject areas

General Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISLPED.2017.8009164

Cite this

Choi, K., Choi, W., Shin, K., & Park, J. (2017). Bit-width reduction and customized register for low cost convolutional neural network accelerator. In ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design Article 8009164 (Proceedings of the International Symposium on Low Power Electronics and Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISLPED.2017.8009164

Bit-width reduction and customized register for low cost convolutional neural network accelerator. / Choi, Kyungrak; Choi, Woong; Shin, Kyungho et al.
ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2017. 8009164 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Choi, K, Choi, W, Shin, K & Park, J 2017, Bit-width reduction and customized register for low cost convolutional neural network accelerator. in ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design., 8009164, Proceedings of the International Symposium on Low Power Electronics and Design, Institute of Electrical and Electronics Engineers Inc., 22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, Province of China, 17/7/24. https://doi.org/10.1109/ISLPED.2017.8009164

Choi K, Choi W, Shin K, Park J. Bit-width reduction and customized register for low cost convolutional neural network accelerator. In ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc. 2017. 8009164. (Proceedings of the International Symposium on Low Power Electronics and Design). doi: 10.1109/ISLPED.2017.8009164

Choi, Kyungrak ; Choi, Woong ; Shin, Kyungho et al. / Bit-width reduction and customized register for low cost convolutional neural network accelerator. ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2017. (Proceedings of the International Symposium on Low Power Electronics and Design).

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abstract = "This paper presents a low area and energy efficient hardware accelerator for the deep convolutional neural networks (CNNs). Based on the multiply-accumulate (MAC) based architecture, three design techniques are proposed to reduce the hardware cost of the convolutional computations. First, to reduce the computational bit-width of convolutions, an adaptive bit-width reduction scheme is proposed based on differential input method. The bit-width reduction approach can reduce the 37 \% of operation bit-width with almost ignorable CNN accuracy degradation. Second, it has been found that adapting bi-directional filtering window in CNN accelerator can considerably reduce the energy for data movement with much smaller number of memory accesses. To expedite the bi-directional filtering operations, we also propose a bidirectional first-input-first-output (bi-FIFO). With SRAM bit-cell layout manner, the proposed bi-FIFO facilitates fast data re-distribution with area and energy efficiency. To verify the effectiveness of the proposed techniques, the AlexNet accelerator has been designed. The numerical results show that the proposed adaptive bit-width reduction scheme achieves 25.9\% and 47.3\% of area and energy savings, respectively. The bi-FIFO based accelerator also achieves 33 \% improved processing time.",

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AU - Shin, Kyungho

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N1 - Funding Information: ACKNOWLEDGMENT This work was supported bythe National Research Foundation of Korea grant funded by the Korea government (NRF-2016 R1A2B4015329 and NRF-2015M3D1A1070465), and the Information Technology Research and Development Program of Korea Evaluation Institute of Industrial Technology [10052716, Design technology development of ultralow voltage operating circuit and IP for smart sensor SoC] Publisher Copyright: © 2017 IEEE.

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N2 - This paper presents a low area and energy efficient hardware accelerator for the deep convolutional neural networks (CNNs). Based on the multiply-accumulate (MAC) based architecture, three design techniques are proposed to reduce the hardware cost of the convolutional computations. First, to reduce the computational bit-width of convolutions, an adaptive bit-width reduction scheme is proposed based on differential input method. The bit-width reduction approach can reduce the 37 % of operation bit-width with almost ignorable CNN accuracy degradation. Second, it has been found that adapting bi-directional filtering window in CNN accelerator can considerably reduce the energy for data movement with much smaller number of memory accesses. To expedite the bi-directional filtering operations, we also propose a bidirectional first-input-first-output (bi-FIFO). With SRAM bit-cell layout manner, the proposed bi-FIFO facilitates fast data re-distribution with area and energy efficiency. To verify the effectiveness of the proposed techniques, the AlexNet accelerator has been designed. The numerical results show that the proposed adaptive bit-width reduction scheme achieves 25.9% and 47.3% of area and energy savings, respectively. The bi-FIFO based accelerator also achieves 33 % improved processing time.

AB - This paper presents a low area and energy efficient hardware accelerator for the deep convolutional neural networks (CNNs). Based on the multiply-accumulate (MAC) based architecture, three design techniques are proposed to reduce the hardware cost of the convolutional computations. First, to reduce the computational bit-width of convolutions, an adaptive bit-width reduction scheme is proposed based on differential input method. The bit-width reduction approach can reduce the 37 % of operation bit-width with almost ignorable CNN accuracy degradation. Second, it has been found that adapting bi-directional filtering window in CNN accelerator can considerably reduce the energy for data movement with much smaller number of memory accesses. To expedite the bi-directional filtering operations, we also propose a bidirectional first-input-first-output (bi-FIFO). With SRAM bit-cell layout manner, the proposed bi-FIFO facilitates fast data re-distribution with area and energy efficiency. To verify the effectiveness of the proposed techniques, the AlexNet accelerator has been designed. The numerical results show that the proposed adaptive bit-width reduction scheme achieves 25.9% and 47.3% of area and energy savings, respectively. The bi-FIFO based accelerator also achieves 33 % improved processing time.

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KW - Deep Neural Network

KW - Energy Efficiency

KW - FIFO

KW - Filter

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KW - Weight

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ER -

Bit-width reduction and customized register for low cost convolutional neural network accelerator

Abstract

Publication series

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Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

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