Body bias generator for leakage power reduction of low-voltage digital logic circuits

Ji Yong Jeong, Gil Su Kim, Jong Pil Son, Woo Jin Rim, Soo Won Kim

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    This paper proposes body-bias generator for leakage power reduction of digital logic circuits which operates at low supply voltage of 0.5V. The proposed circuit adopts double charge pumping scheme to enhance the pumping gain, The proposed circuit is fabricated using 0.13 μm CMOS process and measurement result demonstrates stable operation with body-bias voltage of -0.95V. We apply the proposed circuit to 64-bit carry look-ahead adder to demonstrate its performance. We report that the leakage power of 64-bit carry look-ahead adder can dramatically be reduced by adopting proposed substratebias generator. The estimated leakage power reduction is 90% (T=75°C).

    Original languageEnglish
    Title of host publicationIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation - 16th International Workshop, PATMOS 2006, Proceedings
    PublisherSpringer Verlag
    Pages350-359
    Number of pages10
    ISBN (Print)3540390944, 9783540390947
    DOIs
    Publication statusPublished - 2006
    Event16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006 - Montpellier, France
    Duration: 2006 Sept 132006 Sept 15

    Publication series

    NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
    Volume4148 LNCS
    ISSN (Print)0302-9743
    ISSN (Electronic)1611-3349

    Other

    Other16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006
    Country/TerritoryFrance
    CityMontpellier
    Period06/9/1306/9/15

    ASJC Scopus subject areas

    • Theoretical Computer Science
    • General Computer Science

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