Body bias generator for leakage power reduction of low-voltage digital logic circuits

Ji Yong Jeong; Gil Su Kim; Jong Pil Son; Woo Jin Rim; Soo Won Kim

doi:10.1007/11847083_34

Body bias generator for leakage power reduction of low-voltage digital logic circuits

Ji Yong Jeong, Gil Su Kim, Jong Pil Son, Woo Jin Rim, Soo Won Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes body-bias generator for leakage power reduction of digital logic circuits which operates at low supply voltage of 0.5V. The proposed circuit adopts double charge pumping scheme to enhance the pumping gain, The proposed circuit is fabricated using 0.13 μm CMOS process and measurement result demonstrates stable operation with body-bias voltage of -0.95V. We apply the proposed circuit to 64-bit carry look-ahead adder to demonstrate its performance. We report that the leakage power of 64-bit carry look-ahead adder can dramatically be reduced by adopting proposed substratebias generator. The estimated leakage power reduction is 90% (T=75°C).

Original language	English
Title of host publication	Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation - 16th International Workshop, PATMOS 2006, Proceedings
Publisher	Springer Verlag
Pages	350-359
Number of pages	10
ISBN (Print)	3540390944, 9783540390947
DOIs	https://doi.org/10.1007/11847083_34
Publication status	Published - 2006
Event	16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006 - Montpellier, France Duration: 2006 Sept 13 → 2006 Sept 15

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	4148 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Other

Other	16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006
Country/Territory	France
City	Montpellier
Period	06/9/13 → 06/9/15

ASJC Scopus subject areas

Theoretical Computer Science
General Computer Science

Access to Document

10.1007/11847083_34

Cite this

Jeong, J. Y., Kim, G. S., Son, J. P., Rim, W. J., & Kim, S. W. (2006). Body bias generator for leakage power reduction of low-voltage digital logic circuits. In Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation - 16th International Workshop, PATMOS 2006, Proceedings (pp. 350-359). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4148 LNCS). Springer Verlag. https://doi.org/10.1007/11847083_34

Body bias generator for leakage power reduction of low-voltage digital logic circuits. / Jeong, Ji Yong; Kim, Gil Su; Son, Jong Pil et al.
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation - 16th International Workshop, PATMOS 2006, Proceedings. Springer Verlag, 2006. p. 350-359 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4148 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jeong, JY, Kim, GS, Son, JP, Rim, WJ & Kim, SW 2006, Body bias generator for leakage power reduction of low-voltage digital logic circuits. in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation - 16th International Workshop, PATMOS 2006, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 4148 LNCS, Springer Verlag, pp. 350-359, 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006, Montpellier, France, 06/9/13. https://doi.org/10.1007/11847083_34

Jeong JY, Kim GS, Son JP, Rim WJ, Kim SW. Body bias generator for leakage power reduction of low-voltage digital logic circuits. In Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation - 16th International Workshop, PATMOS 2006, Proceedings. Springer Verlag. 2006. p. 350-359. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/11847083_34

Jeong, Ji Yong ; Kim, Gil Su ; Son, Jong Pil et al. / Body bias generator for leakage power reduction of low-voltage digital logic circuits. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation - 16th International Workshop, PATMOS 2006, Proceedings. Springer Verlag, 2006. pp. 350-359 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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AB - This paper proposes body-bias generator for leakage power reduction of digital logic circuits which operates at low supply voltage of 0.5V. The proposed circuit adopts double charge pumping scheme to enhance the pumping gain, The proposed circuit is fabricated using 0.13 μm CMOS process and measurement result demonstrates stable operation with body-bias voltage of -0.95V. We apply the proposed circuit to 64-bit carry look-ahead adder to demonstrate its performance. We report that the leakage power of 64-bit carry look-ahead adder can dramatically be reduced by adopting proposed substratebias generator. The estimated leakage power reduction is 90% (T=75°C).

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Body bias generator for leakage power reduction of low-voltage digital logic circuits

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