We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (< 450°C), low temperature (< 550°C) in-situ doped S/D selective SiGe epi process, low temperature (< 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.
|Title of host publication||2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2016|
|Event||2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 - Burlingame, United States|
Duration: 2016 Oct 10 → 2016 Oct 13
|Name||2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016|
|Other||2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016|
|Period||16/10/10 → 16/10/13|
Bibliographical noteFunding Information:
This research was supported by the Nano Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (NRF-2015M3A7B7045490).
© 2016 IEEE.
- Epitaxial Growth
- Gate Stack
- Laser Annealing
- Low Temperature Bonding
- Monolithic 3D
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering