Bonding based channel transfer and low temperature process for monolithic 3D integration platform development

Rino Choi; Hyun Yong Yu; Hyungsub Kim; Han Youl Ryu; Hee Kyung Bae; Kevin Kinam Choi; Yong Won Cha; Changhwan Choi

doi:10.1109/S3S.2016.7804407

Bonding based channel transfer and low temperature process for monolithic 3D integration platform development

Rino Choi, Hyun Yong Yu, Hyungsub Kim, Han Youl Ryu, Hee Kyung Bae, Kevin Kinam Choi, Yong Won Cha, Changhwan Choi

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (< 450°C), low temperature (< 550°C) in-situ doped S/D selective SiGe epi process, low temperature (< 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.

Original language	English
Title of host publication	2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509043903
DOIs	https://doi.org/10.1109/S3S.2016.7804407
Publication status	Published - 2016
Event	2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 - Burlingame, United States Duration: 2016 Oct 10 → 2016 Oct 13

Publication series

Name	2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016

Other

Other	2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016
Country/Territory	United States
City	Burlingame
Period	16/10/10 → 16/10/13

Bibliographical note

Funding Information:
This research was supported by the Nano Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (NRF-2015M3A7B7045490).

Publisher Copyright:
© 2016 IEEE.

Keywords

Epitaxial Growth
Gate Stack
Laser Annealing
Low Temperature Bonding
Monolithic 3D

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/S3S.2016.7804407

Cite this

Choi, R., Yu, H. Y., Kim, H., Ryu, H. Y., Bae, H. K., Choi, K. K., Cha, Y. W., & Choi, C. (2016). Bonding based channel transfer and low temperature process for monolithic 3D integration platform development. In 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 Article 7804407 (2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2016.7804407

Bonding based channel transfer and low temperature process for monolithic 3D integration platform development. / Choi, Rino; Yu, Hyun Yong; Kim, Hyungsub et al.
2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7804407 (2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Choi, R, Yu, HY, Kim, H, Ryu, HY, Bae, HK, Choi, KK, Cha, YW & Choi, C 2016, Bonding based channel transfer and low temperature process for monolithic 3D integration platform development. in 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016., 7804407, 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016, Institute of Electrical and Electronics Engineers Inc., 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016, Burlingame, United States, 16/10/10. https://doi.org/10.1109/S3S.2016.7804407

Choi R, Yu HY, Kim H, Ryu HY, Bae HK, Choi KK et al. Bonding based channel transfer and low temperature process for monolithic 3D integration platform development. In 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7804407. (2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016). doi: 10.1109/S3S.2016.7804407

Choi, Rino ; Yu, Hyun Yong ; Kim, Hyungsub et al. / Bonding based channel transfer and low temperature process for monolithic 3D integration platform development. 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016).

@inproceedings{2afbb1c2b3c44d3d8b51cfb31ef20473,

title = "Bonding based channel transfer and low temperature process for monolithic 3D integration platform development",

abstract = "We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (< 450°C), low temperature (< 550°C) in-situ doped S/D selective SiGe epi process, low temperature (< 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.",

keywords = "Epitaxial Growth, Gate Stack, Laser Annealing, Low Temperature Bonding, Monolithic 3D",

author = "Rino Choi and Yu, {Hyun Yong} and Hyungsub Kim and Ryu, {Han Youl} and Bae, {Hee Kyung} and Choi, {Kevin Kinam} and Cha, {Yong Won} and Changhwan Choi",

note = "Funding Information: This research was supported by the Nano Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (NRF-2015M3A7B7045490). Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 ; Conference date: 10-10-2016 Through 13-10-2016",

year = "2016",

doi = "10.1109/S3S.2016.7804407",

language = "English",

series = "2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016",

}

TY - GEN

T1 - Bonding based channel transfer and low temperature process for monolithic 3D integration platform development

AU - Choi, Rino

AU - Yu, Hyun Yong

AU - Kim, Hyungsub

AU - Ryu, Han Youl

AU - Bae, Hee Kyung

AU - Choi, Kevin Kinam

AU - Cha, Yong Won

AU - Choi, Changhwan

N1 - Funding Information: This research was supported by the Nano Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (NRF-2015M3A7B7045490). Publisher Copyright: © 2016 IEEE.

PY - 2016

Y1 - 2016

N2 - We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (< 450°C), low temperature (< 550°C) in-situ doped S/D selective SiGe epi process, low temperature (< 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.

AB - We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (< 450°C), low temperature (< 550°C) in-situ doped S/D selective SiGe epi process, low temperature (< 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.

KW - Epitaxial Growth

KW - Gate Stack

KW - Laser Annealing

KW - Low Temperature Bonding

KW - Monolithic 3D

UR - http://www.scopus.com/inward/record.url?scp=85011317254&partnerID=8YFLogxK

U2 - 10.1109/S3S.2016.7804407

DO - 10.1109/S3S.2016.7804407

M3 - Conference contribution

AN - SCOPUS:85011317254

T3 - 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016

BT - 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016

Y2 - 10 October 2016 through 13 October 2016

ER -

Bonding based channel transfer and low temperature process for monolithic 3D integration platform development

Abstract

Publication series

Other

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this