Abstract
The AE64000 is a 64 bit embedded processor targeting high-end embedded applications such as HDTV, DVD, and 3D graphics. To achieve a higher performance for the AE64000, we design a branch predictor for the processor, and find the optimum parameters for the design through cycle-accurate simulations on SpecINT benchmarks and embedded applications (Dhrystone and Whetstone). In the AE64000, branch prediction is complicated by the instruction folding unit (IFU) of the processor front-end. By predicting on a pre-PC in the IFU, rather than using a PC in the pipeline core, we can effectively eliminate the branch misprediction penalty on a correct prediction. We have developed the AE64000 simulator to evaluate the performance of the designed branch predictor, and selected the optimum branch predictor configuration by considering cost-effectiveness as well as by analyzing the results generated from the AE64000 simulator. The selected branch predictor has been implemented in Verilog and is added to AE64000 pipeline.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 519-522 |
| Number of pages | 4 |
| Volume | 2003-January |
| ISBN (Print) | 0780376595 |
| DOIs | |
| Publication status | Published - 2003 |
| Event | Asia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan Duration: 2003 Jan 21 → 2003 Jan 24 |
Other
| Other | Asia and South Pacific Design Automation Conference, ASP-DAC 2003 |
|---|---|
| Country/Territory | Japan |
| City | Kitakyushu |
| Period | 03/1/21 → 03/1/24 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Science Applications
- Computer Graphics and Computer-Aided Design