Capless Low-Dropout Regulator with a Dual Feedback Loop and Voltage Dampers

Yun Seong Lee; Yun Chan Im; Hyunjin Lee; Yong Sin Kim

doi:10.1109/ISOCC56007.2022.10031484

Capless Low-Dropout Regulator with a Dual Feedback Loop and Voltage Dampers

Yun Seong Lee
, Yun Chan Im
, Hyunjin Lee
, Yong Sin Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper presents a capless low-dropout regulator (LDO) using a dual feedback loop and voltage dampers for fast load transient. For small load transient, a low-speed error amplifier controls the gate of a pass transistor and allows for high DC gain. To extend bandwidth, most of power budget is allocated to the high-speed loop in which the body terminal of the pass transistor is controlled. When large load transient detected, the proposed voltage dampers are turned on temporarily and control the gate of the pass transistor to regulate the output. The proposed LDO regulator is fabricated in a 0.18 μ m CMOS process with the active area of 0.027 mm2 and on-chip capacitance of 9.33 pF.Experimental results show that the proposed LDO is superior to others by having figure-of-merit (FOM) of 1.264 mV/μ m2 at the quiescent current of 29 μ A.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2022, ISOCC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	298-299
Number of pages	2
ISBN (Electronic)	9781665459716
DOIs	https://doi.org/10.1109/ISOCC56007.2022.10031484
Publication status	Published - 2022
Event	19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of Duration: 2022 Oct 19 → 2022 Oct 22

Publication series

Name	Proceedings - International SoC Design Conference 2022, ISOCC 2022

Conference

Conference	19th International System-on-Chip Design Conference, ISOCC 2022
Country/Territory	Korea, Republic of
City	Gangneung-si
Period	22/10/19 → 22/10/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Keywords

Body-bias
Dual-loop
Fast load transient
Low-dropout regulator
Voltage damper

ASJC Scopus subject areas

Artificial Intelligence
Computer Science Applications
Hardware and Architecture
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ISOCC56007.2022.10031484

Cite this

Lee, Y. S., Im, Y. C., Lee, H., & Kim, Y. S. (2022). Capless Low-Dropout Regulator with a Dual Feedback Loop and Voltage Dampers. In Proceedings - International SoC Design Conference 2022, ISOCC 2022 (pp. 298-299). (Proceedings - International SoC Design Conference 2022, ISOCC 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC56007.2022.10031484

Capless Low-Dropout Regulator with a Dual Feedback Loop and Voltage Dampers. / Lee, Yun Seong; Im, Yun Chan; Lee, Hyunjin et al.
Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 298-299 (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, YS, Im, YC, Lee, H & Kim, YS 2022, Capless Low-Dropout Regulator with a Dual Feedback Loop and Voltage Dampers. in Proceedings - International SoC Design Conference 2022, ISOCC 2022. Proceedings - International SoC Design Conference 2022, ISOCC 2022, Institute of Electrical and Electronics Engineers Inc., pp. 298-299, 19th International System-on-Chip Design Conference, ISOCC 2022, Gangneung-si, Korea, Republic of, 22/10/19. https://doi.org/10.1109/ISOCC56007.2022.10031484

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title = "Capless Low-Dropout Regulator with a Dual Feedback Loop and Voltage Dampers",

abstract = "This paper presents a capless low-dropout regulator (LDO) using a dual feedback loop and voltage dampers for fast load transient. For small load transient, a low-speed error amplifier controls the gate of a pass transistor and allows for high DC gain. To extend bandwidth, most of power budget is allocated to the high-speed loop in which the body terminal of the pass transistor is controlled. When large load transient detected, the proposed voltage dampers are turned on temporarily and control the gate of the pass transistor to regulate the output. The proposed LDO regulator is fabricated in a 0.18 μ m CMOS process with the active area of 0.027 mm2 and on-chip capacitance of 9.33 pF.Experimental results show that the proposed LDO is superior to others by having figure-of-merit (FOM) of 1.264 mV/μ m2 at the quiescent current of 29 μ A.",

keywords = "Body-bias, Dual-loop, Fast load transient, Low-dropout regulator, Voltage damper",

author = "Lee, \{Yun Seong\} and Im, \{Yun Chan\} and Hyunjin Lee and Kim, \{Yong Sin\}",

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doi = "10.1109/ISOCC56007.2022.10031484",

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AU - Lee, Hyunjin

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PY - 2022

Y1 - 2022

N2 - This paper presents a capless low-dropout regulator (LDO) using a dual feedback loop and voltage dampers for fast load transient. For small load transient, a low-speed error amplifier controls the gate of a pass transistor and allows for high DC gain. To extend bandwidth, most of power budget is allocated to the high-speed loop in which the body terminal of the pass transistor is controlled. When large load transient detected, the proposed voltage dampers are turned on temporarily and control the gate of the pass transistor to regulate the output. The proposed LDO regulator is fabricated in a 0.18 μ m CMOS process with the active area of 0.027 mm2 and on-chip capacitance of 9.33 pF.Experimental results show that the proposed LDO is superior to others by having figure-of-merit (FOM) of 1.264 mV/μ m2 at the quiescent current of 29 μ A.

AB - This paper presents a capless low-dropout regulator (LDO) using a dual feedback loop and voltage dampers for fast load transient. For small load transient, a low-speed error amplifier controls the gate of a pass transistor and allows for high DC gain. To extend bandwidth, most of power budget is allocated to the high-speed loop in which the body terminal of the pass transistor is controlled. When large load transient detected, the proposed voltage dampers are turned on temporarily and control the gate of the pass transistor to regulate the output. The proposed LDO regulator is fabricated in a 0.18 μ m CMOS process with the active area of 0.027 mm2 and on-chip capacitance of 9.33 pF.Experimental results show that the proposed LDO is superior to others by having figure-of-merit (FOM) of 1.264 mV/μ m2 at the quiescent current of 29 μ A.

KW - Body-bias

KW - Dual-loop

KW - Fast load transient

KW - Low-dropout regulator

KW - Voltage damper

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M3 - Conference contribution

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BT - Proceedings - International SoC Design Conference 2022, ISOCC 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 19th International System-on-Chip Design Conference, ISOCC 2022

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ER -

Capless Low-Dropout Regulator with a Dual Feedback Loop and Voltage Dampers

Abstract

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Bibliographical note

Keywords

ASJC Scopus subject areas

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