Centaur: a hybrid network-on-chip architecture utilizing micro-network fusion

Junghee Lee, Chrysostomos Nicopoulos, Hyung Gyu Lee, Jongman Kim

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


The escalating proliferation of multicore chips has accentuated the criticality of the on-chip network. Packet-based networks-on-chip (NoC) have emerged as the de facto interconnect of future chip multi-processors (CMP). On-chip traffic comprises a mixture of data and control messages from the cache coherence protocol. Given the latency-criticality of control messages, in this paper we aim to optimize their delivery times. Instead of treating the on-chip router as a monolithic component, we advocate the introduction of an ultra-low-latency ring-inspired (i.e., utilizing ring primitive building blocks) support micro-network that is optimized for control messages. This $$\upmu $$μNoC is fused with a throughput-driven conventional NoC router to form a hybrid architecture, called Centaur, which maintains separate data paths and control logic for the two fused networks. Full-system simulation results from a 64-core CMP indicate that the proposed fused Centaur router improves overall system performance by up to 26 %, as compared to a state-of-the-art router implementation. Furthermore, hardware synthesis results using commercial 65 nm libraries indicate that Centaur’s area and power overheads are 9 and 3 %, respectively, as compared to a baseline router design. More importantly, the new design does not affect the router’s critical path.

Original languageEnglish
Pages (from-to)121-139
Number of pages19
JournalDesign Automation for Embedded Systems
Issue number3-4
Publication statusPublished - 2014 Sept 20
Externally publishedYes


  • Interconnection networks
  • Networks-on-chip
  • Segregated/separated networks

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture


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