Abstract
A D-band low-noise amplifier (LNA) has been developed based on a 65-nm CMOS technology, which showed a measured peak gain of 16.1 dB at 134.5 GHz. The noise property of the fabricated amplifier was characterized with two different noise measurement techniques: the cryogenic Y-factor method and the N-times power method. The two methods showed a minimum value of the noise figure of 10.7 dB and 14.7 dB, respectively.
Original language | English |
---|---|
Pages (from-to) | 536-540 |
Number of pages | 5 |
Journal | Journal of Semiconductor Technology and Science |
Volume | 18 |
Issue number | 4 |
DOIs | |
Publication status | Published - 2018 Aug |
Bibliographical note
Funding Information:This work wasupportedbytheNational Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (NRF-2015R1A2A1A05001836).
Publisher Copyright:
© 2018, Institute of Electronics Engineers of Korea. All rights reserved.
Keywords
- 65 nm CMOS
- Low-noise amplifier
- N-times power method
- Noise
- Y-factor method
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering