Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM

Gyuseong Kang; Jongsun Park

doi:10.1109/TVLSI.2019.2901291

Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM

Gyuseong Kang, Jongsun Park

Research output: Contribution to journal › Article › peer-review

12 Citations (Scopus)

Abstract

In spin-orbit torque magnetic random access memory (SOT-MRAM), as write energy is much larger than read energy, writing data to memory only when the new data is different from the stored data can lead to considerable write energy savings. In this paper, we propose three low-power techniques that can significantly reduce write energy in the read-compare-write process. In the proposed approaches, redundant charge in read operation has been efficiently reused to generate a negative voltage for write assistance, which leads to short write time. A selective precharging technique is also proposed to minimize the voltage swings between read and write operations. In addition, asymmetric write current due to source degeneration of write transistor can be resolved with the write voltage suppression scheme. Our circuit simulations with 65-nm CMOS technology show that when the stored data and new data are the same, up to 61% of write energy savings have been achieved compared with the conventional 2T-1MTJ cell. When the proposed SOT-MRAM is used as L3 caches of X86 processor, the gem5 simulations also show that average 48.2% of write energy savings can be achieved in various workloads of SPEC2006.

Original language	English
Article number	8667706
Pages (from-to)	1343-1352
Number of pages	10
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	27
Issue number	6
DOIs	https://doi.org/10.1109/TVLSI.2019.2901291
Publication status	Published - 2019 Jun

Bibliographical note

Funding Information:
Manuscript received September 18, 2018; revised January 10, 2019; accepted February 11, 2019. Date of publication March 15, 2019; date of current version May 22, 2019. This work was supported in part by the National Research Foundation of Korea under Grant NRF-2016R1A2B4015329 and Grant NRF-2015M3D1A1070465, and in part by the Ministry of Science and ICT, South Korea, through the Information Technology Research Center support Program supervised by the Institute for Information & communications Technology Promotion (IITP) under Grant IITP-2018-0-01433. (Corresponding author: Jongsun Park.) The authors are with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]; [email protected]).

Publisher Copyright:
© 2019 IEEE.

Keywords

SOT magnetic random access memory (SOT-MRAM)
Spin-orbit torque (SOT)
write power reduction

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2019.2901291

Cite this

@article{f99ab9ffeaac4191a1b004271d414388,

title = "Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM",

abstract = "In spin-orbit torque magnetic random access memory (SOT-MRAM), as write energy is much larger than read energy, writing data to memory only when the new data is different from the stored data can lead to considerable write energy savings. In this paper, we propose three low-power techniques that can significantly reduce write energy in the read-compare-write process. In the proposed approaches, redundant charge in read operation has been efficiently reused to generate a negative voltage for write assistance, which leads to short write time. A selective precharging technique is also proposed to minimize the voltage swings between read and write operations. In addition, asymmetric write current due to source degeneration of write transistor can be resolved with the write voltage suppression scheme. Our circuit simulations with 65-nm CMOS technology show that when the stored data and new data are the same, up to 61% of write energy savings have been achieved compared with the conventional 2T-1MTJ cell. When the proposed SOT-MRAM is used as L3 caches of X86 processor, the gem5 simulations also show that average 48.2% of write energy savings can be achieved in various workloads of SPEC2006.",

keywords = "SOT magnetic random access memory (SOT-MRAM), Spin-orbit torque (SOT), write power reduction",

author = "Gyuseong Kang and Jongsun Park",

note = "Funding Information: Manuscript received September 18, 2018; revised January 10, 2019; accepted February 11, 2019. Date of publication March 15, 2019; date of current version May 22, 2019. This work was supported in part by the National Research Foundation of Korea under Grant NRF-2016R1A2B4015329 and Grant NRF-2015M3D1A1070465, and in part by the Ministry of Science and ICT, South Korea, through the Information Technology Research Center support Program supervised by the Institute for Information & communications Technology Promotion (IITP) under Grant IITP-2018-0-01433. (Corresponding author: Jongsun Park.) The authors are with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]; [email protected]). Publisher Copyright: {\textcopyright} 2019 IEEE.",

year = "2019",

month = jun,

doi = "10.1109/TVLSI.2019.2901291",

language = "English",

volume = "27",

pages = "1343--1352",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM

AU - Kang, Gyuseong

AU - Park, Jongsun

N1 - Funding Information: Manuscript received September 18, 2018; revised January 10, 2019; accepted February 11, 2019. Date of publication March 15, 2019; date of current version May 22, 2019. This work was supported in part by the National Research Foundation of Korea under Grant NRF-2016R1A2B4015329 and Grant NRF-2015M3D1A1070465, and in part by the Ministry of Science and ICT, South Korea, through the Information Technology Research Center support Program supervised by the Institute for Information & communications Technology Promotion (IITP) under Grant IITP-2018-0-01433. (Corresponding author: Jongsun Park.) The authors are with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]; [email protected]). Publisher Copyright: © 2019 IEEE.

PY - 2019/6

Y1 - 2019/6

N2 - In spin-orbit torque magnetic random access memory (SOT-MRAM), as write energy is much larger than read energy, writing data to memory only when the new data is different from the stored data can lead to considerable write energy savings. In this paper, we propose three low-power techniques that can significantly reduce write energy in the read-compare-write process. In the proposed approaches, redundant charge in read operation has been efficiently reused to generate a negative voltage for write assistance, which leads to short write time. A selective precharging technique is also proposed to minimize the voltage swings between read and write operations. In addition, asymmetric write current due to source degeneration of write transistor can be resolved with the write voltage suppression scheme. Our circuit simulations with 65-nm CMOS technology show that when the stored data and new data are the same, up to 61% of write energy savings have been achieved compared with the conventional 2T-1MTJ cell. When the proposed SOT-MRAM is used as L3 caches of X86 processor, the gem5 simulations also show that average 48.2% of write energy savings can be achieved in various workloads of SPEC2006.

AB - In spin-orbit torque magnetic random access memory (SOT-MRAM), as write energy is much larger than read energy, writing data to memory only when the new data is different from the stored data can lead to considerable write energy savings. In this paper, we propose three low-power techniques that can significantly reduce write energy in the read-compare-write process. In the proposed approaches, redundant charge in read operation has been efficiently reused to generate a negative voltage for write assistance, which leads to short write time. A selective precharging technique is also proposed to minimize the voltage swings between read and write operations. In addition, asymmetric write current due to source degeneration of write transistor can be resolved with the write voltage suppression scheme. Our circuit simulations with 65-nm CMOS technology show that when the stored data and new data are the same, up to 61% of write energy savings have been achieved compared with the conventional 2T-1MTJ cell. When the proposed SOT-MRAM is used as L3 caches of X86 processor, the gem5 simulations also show that average 48.2% of write energy savings can be achieved in various workloads of SPEC2006.

KW - SOT magnetic random access memory (SOT-MRAM)

KW - Spin-orbit torque (SOT)

KW - write power reduction

UR - http://www.scopus.com/inward/record.url?scp=85066400090&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2019.2901291

DO - 10.1109/TVLSI.2019.2901291

M3 - Article

AN - SCOPUS:85066400090

SN - 1063-8210

VL - 27

SP - 1343

EP - 1352

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 6

M1 - 8667706

ER -

Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM

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Keywords

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