Charge-trap flash memory devices fabricated with nano-scale patterns on the Si 3N 4 trapping layer

Ho Myoung An; Kyong Heon Kim; Hee Dong Kim; Won Ju Cho; Tae Geun Kim

doi:10.1109/SNW.2012.6243350

Charge-trap flash memory devices fabricated with nano-scale patterns on the Si ₃N ₄ trapping layer

Ho Myoung An, Kyong Heon Kim, Hee Dong Kim, Won Ju Cho, Tae Geun Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

We proposed a novel CTF memory structure with surface patterned Si ₃N ₄ trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si ₃N ₄ trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable reliability, including data retention of 10 years and endurance of 10 ⁴ P/E cycles, was obtained.

Original language	English
Title of host publication	2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012
DOIs	https://doi.org/10.1109/SNW.2012.6243350
Publication status	Published - 2012
Event	2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012 - Honolulu, HI, United States Duration: 2012 Jun 10 → 2012 Jun 11

Publication series

Name	2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012

Other

Other	2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012
Country/Territory	United States
City	Honolulu, HI
Period	12/6/10 → 12/6/11

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/SNW.2012.6243350

Cite this

An, HM, Kim, KH, Kim, HD, Cho, WJ & Kim, TG 2012, Charge-trap flash memory devices fabricated with nano-scale patterns on the Si ₃N ₄ trapping layer. in 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012., 6243350, 2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012, 2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012, Honolulu, HI, United States, 12/6/10. https://doi.org/10.1109/SNW.2012.6243350

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abstract = "We proposed a novel CTF memory structure with surface patterned Si 3N 4 trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si 3N 4 trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable reliability, including data retention of 10 years and endurance of 10 4 P/E cycles, was obtained.",

author = "An, {Ho Myoung} and Kim, {Kyong Heon} and Kim, {Hee Dong} and Cho, {Won Ju} and Kim, {Tae Geun}",

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AB - We proposed a novel CTF memory structure with surface patterned Si 3N 4 trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si 3N 4 trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable reliability, including data retention of 10 years and endurance of 10 4 P/E cycles, was obtained.

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