Circuit design techniques for multimedia wireline communications

Chulwoo Kim

doi:10.1109/ASICON.2015.7516917

Circuit design techniques for multimedia wireline communications

Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents several circuit design techniques for multimedia wireline interfaces. A 7.5 Gb/s transceiver with pre-emphasis and bandwidth (BW)-shifting techniques are introduced. By applying dynamic calibration technique for pre-emphasis, the measured transmitter eye-opening is improved by 24 %. BW shifting clock generator achieves the jitter reduction of 43%. In addition, a wide input range comparator for 11.2 Gb/s low-voltage-differential-swing (LVDS) multi-channel receiver is also introduced. The comparator achieves 81.9 % of the received data RMS jitter reduction for the LVDS receiver.

Original language	English
Title of host publication	Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479984831
DOIs	https://doi.org/10.1109/ASICON.2015.7516917
Publication status	Published - 2016 Jul 19
Event	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China Duration: 2015 Nov 3 → 2015 Nov 6

Other

Other	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
Country/Territory	China
City	Chengdu
Period	15/11/3 → 15/11/6

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ASICON.2015.7516917

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Kim, C 2016, Circuit design techniques for multimedia wireline communications. in Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015., 7516917, Institute of Electrical and Electronics Engineers Inc., 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, Chengdu, China, 15/11/3. https://doi.org/10.1109/ASICON.2015.7516917

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AB - This paper presents several circuit design techniques for multimedia wireline interfaces. A 7.5 Gb/s transceiver with pre-emphasis and bandwidth (BW)-shifting techniques are introduced. By applying dynamic calibration technique for pre-emphasis, the measured transmitter eye-opening is improved by 24 %. BW shifting clock generator achieves the jitter reduction of 43%. In addition, a wide input range comparator for 11.2 Gb/s low-voltage-differential-swing (LVDS) multi-channel receiver is also introduced. The comparator achieves 81.9 % of the received data RMS jitter reduction for the LVDS receiver.

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Circuit design techniques for multimedia wireline communications

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