CMOS 120 GHz phase-locked loops based on two different VCO topologies

Junghwan Yoo, Jae Sung Rieh

    Research output: Contribution to journalArticlepeer-review

    3 Citations (Scopus)

    Abstract

    This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. The measured locking ranges of the LC cross-coupled VCO-based phase-locked loop (PLL1) and the Colpitts VCO-based phase-locked loop (PLL2) are 119.84-122.61 GHz and 126.53-129.29 GHz, respectively. Th e output powers of PLL1 and PLL2 are -8.6 dBm and -10.5 dBm with DC power consumptions of 127.3 mW and 142.8 mW, respectively. The measured phase noise of PLL1 is -59.2 at 10 kHz offset and -104.5 at 10 MHz offset, and the phase noise of PLL2 is -60.9 dBc/Hz at 10 kHz offset and -104.4 dBc/Hz at 10 MHz offset. The chip sizes are 1,080 μm × 760 μm (PLL1) and 1,100 μm × 800 μm (PLL2), including the probing pads.

    Original languageEnglish
    Pages (from-to)98-104
    Number of pages7
    JournalJournal of Electromagnetic Engineering and Science
    Volume17
    Issue number2
    DOIs
    Publication statusPublished - 2017 Apr 1

    Bibliographical note

    Funding Information:
    This work was supported by the National Research Foundation under a grant funded by the Korea Government (MSIP) (NRF-2015R1A2A1A05001836).

    Keywords

    • CMOS
    • Frequency Doubler
    • Phase-Locked Loop (PLL)
    • Signal Source
    • Voltage-Controlled Oscillator (VCO)

    ASJC Scopus subject areas

    • Radiation
    • Instrumentation
    • Computer Networks and Communications
    • Electrical and Electronic Engineering

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