Compact Implementations of HIGHT Block Cipher on IoT Platforms

Bohun Kim; Junghoon Cho; Byungjun Choi; Jongsun Park; Hwajeong Seo

doi:10.1155/2019/5323578

Compact Implementations of HIGHT Block Cipher on IoT Platforms

Bohun Kim
, Junghoon Cho
, Byungjun Choi
, Jongsun Park
, Hwajeong Seo^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

23 Citations (Scopus)

Abstract

Recent lightweight block cipher competition (FELICS Triathlon) evaluates efficient implementations of block ciphers for Internet of things (IoT) environment. In the competition, the implementation of HIGHT block cipher achieved the most efficient lightweight block cipher, in terms of code size (ROM), memory (RAM), and execution time. In this paper, we further investigate lightweight features of HIGHT block cipher and present the optimized implementations of both software and hardware for low-end IoT platforms, including resource-constrained devices (8-bit AVR and 32-bit ARM Cortex-M3) and application-specific integrated circuit (ASIC). By using proposed optimization methods, the implemented HIGHT block cipher shows better performance compared to previous state-of-the-art implementations.

Original language	English
Article number	5323578
Journal	Security and Communication Networks
Volume	2019
DOIs	https://doi.org/10.1155/2019/5323578
Publication status	Published - 2019

Bibliographical note

Funding Information:
.is work was supported in part by the Military Crypto Research Center (UD170109ED) funded by the Defense Acquisition Program Administration (DAPA) and Agency for Defense Development (ADD).

Publisher Copyright:
© 2019 Bohun Kim et al.

ASJC Scopus subject areas

Information Systems
Computer Networks and Communications

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abstract = "Recent lightweight block cipher competition (FELICS Triathlon) evaluates efficient implementations of block ciphers for Internet of things (IoT) environment. In the competition, the implementation of HIGHT block cipher achieved the most efficient lightweight block cipher, in terms of code size (ROM), memory (RAM), and execution time. In this paper, we further investigate lightweight features of HIGHT block cipher and present the optimized implementations of both software and hardware for low-end IoT platforms, including resource-constrained devices (8-bit AVR and 32-bit ARM Cortex-M3) and application-specific integrated circuit (ASIC). By using proposed optimization methods, the implemented HIGHT block cipher shows better performance compared to previous state-of-the-art implementations.",

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AU - Seo, Hwajeong

N1 - Funding Information: .is work was supported in part by the Military Crypto Research Center (UD170109ED) funded by the Defense Acquisition Program Administration (DAPA) and Agency for Defense Development (ADD). Publisher Copyright: © 2019 Bohun Kim et al.

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Compact Implementations of HIGHT Block Cipher on IoT Platforms

Abstract

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