Computation sharing programmable FIR filter for low-power and high-performance applications

Jongsun Park, Woopyo Jeong, Hamid Mahmoodi-Meimand, Yongtao Wang, Hunsoo Choo, Kaushik Roy

Research output: Contribution to journalArticlepeer-review

86 Citations (Scopus)


This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm2 area.

Original languageEnglish
Pages (from-to)348-357
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Issue number2
Publication statusPublished - 2004 Feb
Externally publishedYes


  • Computation sharing
  • Dual transition skewed logic
  • Programmable finite impulse response (FIR) filter

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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