TY - GEN
T1 - Content addressable memory based binarized neural network accelerator using time-domain signal processing
AU - Choi, Woong
AU - Jeong, Kwanghyo
AU - Choi, Kyungrak
AU - Lee, Kyeongho
AU - Park, Jongsun
N1 - Funding Information:
This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIP) (No. 2016R1A2B4015329 and NRF-2015M3D1A1070465) and the Industrial Strategic Technology Development Program(10077445, Development of SoC technology based on Spiking Neural Cell for smart mobile and IoT Devices) funded By the Ministry of Trade, Industry ? Energy(MOTIE, Korea).
Publisher Copyright:
© 2018 Association for Computing Machinery.
PY - 2018/6/24
Y1 - 2018/6/24
N2 - Binarized neural network (BNN) is one of the most promising solution for low-cost convolutional neural network acceleration. Since BNN is based on binarized bit-level operations, there exist great opportunities to reduce power-hungry data transfers and complex arithmetic operations. In this paper, we propose a content addressable memory (CAM) based BNN accelerator. By using time-domain signal processing, the huge convolution operations of BNN can be effectively replaced to the CAM search operation. In addition, thanks to fully parallel search of CAM, the parallel convolution operations for non-overlapped filtering window is enabled for high throughput data processing. To verify the effectiveness of the proposed CAM based BNN accelerator, the convolutional layer of LeNet-5 model has been implemented using 65nm CMOS technology. The implementation results show that the proposed BNN accelerator achieves 9.4% and 38.5% of area and energy savings, respectively. The parallel convolution operation of the proposed approach also shows 2.4x improved processing time.
AB - Binarized neural network (BNN) is one of the most promising solution for low-cost convolutional neural network acceleration. Since BNN is based on binarized bit-level operations, there exist great opportunities to reduce power-hungry data transfers and complex arithmetic operations. In this paper, we propose a content addressable memory (CAM) based BNN accelerator. By using time-domain signal processing, the huge convolution operations of BNN can be effectively replaced to the CAM search operation. In addition, thanks to fully parallel search of CAM, the parallel convolution operations for non-overlapped filtering window is enabled for high throughput data processing. To verify the effectiveness of the proposed CAM based BNN accelerator, the convolutional layer of LeNet-5 model has been implemented using 65nm CMOS technology. The implementation results show that the proposed BNN accelerator achieves 9.4% and 38.5% of area and energy savings, respectively. The parallel convolution operation of the proposed approach also shows 2.4x improved processing time.
KW - Binarized neural network
KW - Content addressable memory
KW - Timedomain signal processing
UR - http://www.scopus.com/inward/record.url?scp=85053683828&partnerID=8YFLogxK
U2 - 10.1145/3195970.3196014
DO - 10.1145/3195970.3196014
M3 - Conference contribution
AN - SCOPUS:85053683828
SN - 9781450357005
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 55th Annual Design Automation Conference, DAC 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 55th Annual Design Automation Conference, DAC 2018
Y2 - 24 June 2018 through 29 June 2018
ER -