Content addressable memory based binarized neural network accelerator using time-domain signal processing

Woong Choi; Kwanghyo Jeong; Kyungrak Choi; Kyeongho Lee; Jongsun Park

doi:10.1145/3195970.3196014

Content addressable memory based binarized neural network accelerator using time-domain signal processing

Woong Choi, Kwanghyo Jeong, Kyungrak Choi, Kyeongho Lee, Jongsun Park

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Citations (Scopus)

Abstract

Binarized neural network (BNN) is one of the most promising solution for low-cost convolutional neural network acceleration. Since BNN is based on binarized bit-level operations, there exist great opportunities to reduce power-hungry data transfers and complex arithmetic operations. In this paper, we propose a content addressable memory (CAM) based BNN accelerator. By using time-domain signal processing, the huge convolution operations of BNN can be effectively replaced to the CAM search operation. In addition, thanks to fully parallel search of CAM, the parallel convolution operations for non-overlapped filtering window is enabled for high throughput data processing. To verify the effectiveness of the proposed CAM based BNN accelerator, the convolutional layer of LeNet-5 model has been implemented using 65nm CMOS technology. The implementation results show that the proposed BNN accelerator achieves 9.4% and 38.5% of area and energy savings, respectively. The parallel convolution operation of the proposed approach also shows 2.4x improved processing time.

Original language	English
Title of host publication	Proceedings of the 55th Annual Design Automation Conference, DAC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781450357005
DOIs	https://doi.org/10.1145/3195970.3196014
Publication status	Published - 2018 Jun 24
Event	55th Annual Design Automation Conference, DAC 2018 - San Francisco, United States Duration: 2018 Jun 24 → 2018 Jun 29

Publication series

Name	Proceedings - Design Automation Conference
Volume	Part F137710
ISSN (Print)	0738-100X

Other

Other	55th Annual Design Automation Conference, DAC 2018
Country/Territory	United States
City	San Francisco
Period	18/6/24 → 18/6/29

Bibliographical note

Publisher Copyright:
© 2018 Association for Computing Machinery.

Keywords

Binarized neural network
Content addressable memory
Timedomain signal processing

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modelling and Simulation

Access to Document

10.1145/3195970.3196014

Cite this

Choi, W., Jeong, K., Choi, K., Lee, K., & Park, J. (2018). Content addressable memory based binarized neural network accelerator using time-domain signal processing. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018 Article a138 (Proceedings - Design Automation Conference; Vol. Part F137710). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3195970.3196014

Content addressable memory based binarized neural network accelerator using time-domain signal processing. / Choi, Woong; Jeong, Kwanghyo; Choi, Kyungrak et al.
Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. a138 (Proceedings - Design Automation Conference; Vol. Part F137710).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Choi, W, Jeong, K, Choi, K, Lee, K & Park, J 2018, Content addressable memory based binarized neural network accelerator using time-domain signal processing. in Proceedings of the 55th Annual Design Automation Conference, DAC 2018., a138, Proceedings - Design Automation Conference, vol. Part F137710, Institute of Electrical and Electronics Engineers Inc., 55th Annual Design Automation Conference, DAC 2018, San Francisco, United States, 18/6/24. https://doi.org/10.1145/3195970.3196014

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keywords = "Binarized neural network, Content addressable memory, Timedomain signal processing",

author = "Woong Choi and Kwanghyo Jeong and Kyungrak Choi and Kyeongho Lee and Jongsun Park",

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N2 - Binarized neural network (BNN) is one of the most promising solution for low-cost convolutional neural network acceleration. Since BNN is based on binarized bit-level operations, there exist great opportunities to reduce power-hungry data transfers and complex arithmetic operations. In this paper, we propose a content addressable memory (CAM) based BNN accelerator. By using time-domain signal processing, the huge convolution operations of BNN can be effectively replaced to the CAM search operation. In addition, thanks to fully parallel search of CAM, the parallel convolution operations for non-overlapped filtering window is enabled for high throughput data processing. To verify the effectiveness of the proposed CAM based BNN accelerator, the convolutional layer of LeNet-5 model has been implemented using 65nm CMOS technology. The implementation results show that the proposed BNN accelerator achieves 9.4% and 38.5% of area and energy savings, respectively. The parallel convolution operation of the proposed approach also shows 2.4x improved processing time.

AB - Binarized neural network (BNN) is one of the most promising solution for low-cost convolutional neural network acceleration. Since BNN is based on binarized bit-level operations, there exist great opportunities to reduce power-hungry data transfers and complex arithmetic operations. In this paper, we propose a content addressable memory (CAM) based BNN accelerator. By using time-domain signal processing, the huge convolution operations of BNN can be effectively replaced to the CAM search operation. In addition, thanks to fully parallel search of CAM, the parallel convolution operations for non-overlapped filtering window is enabled for high throughput data processing. To verify the effectiveness of the proposed CAM based BNN accelerator, the convolutional layer of LeNet-5 model has been implemented using 65nm CMOS technology. The implementation results show that the proposed BNN accelerator achieves 9.4% and 38.5% of area and energy savings, respectively. The parallel convolution operation of the proposed approach also shows 2.4x improved processing time.

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Content addressable memory based binarized neural network accelerator using time-domain signal processing

Abstract

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Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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