Covered source-channel tunnel field-effect transistors with trench gate structures

Sola Woo; Sangsig Kim

doi:10.1109/TNANO.2018.2882859

Covered source-channel tunnel field-effect transistors with trench gate structures

Sola Woo, Sangsig Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

18 Citations (Scopus)

Abstract

We propose a new design for covered source-channel tunnel field-effect transistors (CSC-TFETs) with trench gate structures. The I-V characteristics, on/off current ratio, subthreshold swing, and band-to-band tunneling rate are analyzed using a commercial device simulator. Our proposed CSC-TFETs exhibit an on/off current ratio of approximately 10¹⁰, an on-current of approximately 10^-5 A/μm at room temperature, and a subthreshold swing of less than 40 mV/decade. In addition, the on-current of the CSC-TFETs is ∼233 times that of conventional TFETs, demonstrating that the switching characteristics are superior to those of other silicon-based TFETs. Moreover, a CSC-TFET inverter is characterized by SPICE calibration and provides a high frequency of approximately 1 GHz at a supply voltage of 1.0 V.

Original language	English
Article number	8554273
Pages (from-to)	114-118
Number of pages	5
Journal	IEEE Transactions on Nanotechnology
Volume	18
DOIs	https://doi.org/10.1109/TNANO.2018.2882859
Publication status	Published - 2019

Bibliographical note

Funding Information:
Manuscript received October 16, 2018; accepted November 17, 2018. Date of publication November 30, 2018; date of current version December 31, 2018. This work was supported in part by the National Research Foundation of Korea Grant funded by the Korean Government (MSIP) (NRF-2013R1A2A1A03070750, NRF-2015R1A2A1A15055437), in part by the Ministry of Trade, Industry and Energy (MOTIE, South Korea) under Industrial Strategic Technology Development Program, (10067791, “Development of fabrication and device structure of feedback Si channel 1T-SRAM for artificial intelligence”), in part by the Brain Korea 21 Plus Project in 2018, and in part by the Samsung Electronics. The review of this paper was arranged by Associate Editor S. Mohanty. (Corresponding author: Sangsig Kim.) The authors are with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail:,[email protected]; sangsig@korea. ac.kr).

Publisher Copyright:
© 2002-2012 IEEE.

Keywords

SPICE model
TCAD simulation
Tunnel field-effect transistors
covered source-channel TFET
trench gate

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

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10.1109/TNANO.2018.2882859

Cite this

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title = "Covered source-channel tunnel field-effect transistors with trench gate structures",

abstract = "We propose a new design for covered source-channel tunnel field-effect transistors (CSC-TFETs) with trench gate structures. The I-V characteristics, on/off current ratio, subthreshold swing, and band-to-band tunneling rate are analyzed using a commercial device simulator. Our proposed CSC-TFETs exhibit an on/off current ratio of approximately 1010, an on-current of approximately 10-5 A/μm at room temperature, and a subthreshold swing of less than 40 mV/decade. In addition, the on-current of the CSC-TFETs is ∼233 times that of conventional TFETs, demonstrating that the switching characteristics are superior to those of other silicon-based TFETs. Moreover, a CSC-TFET inverter is characterized by SPICE calibration and provides a high frequency of approximately 1 GHz at a supply voltage of 1.0 V.",

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note = "Funding Information: Manuscript received October 16, 2018; accepted November 17, 2018. Date of publication November 30, 2018; date of current version December 31, 2018. This work was supported in part by the National Research Foundation of Korea Grant funded by the Korean Government (MSIP) (NRF-2013R1A2A1A03070750, NRF-2015R1A2A1A15055437), in part by the Ministry of Trade, Industry and Energy (MOTIE, South Korea) under Industrial Strategic Technology Development Program, (10067791, “Development of fabrication and device structure of feedback Si channel 1T-SRAM for artificial intelligence”), in part by the Brain Korea 21 Plus Project in 2018, and in part by the Samsung Electronics. The review of this paper was arranged by Associate Editor S. Mohanty. (Corresponding author: Sangsig Kim.) The authors are with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail:,[email protected]; sangsig@korea. ac.kr). Publisher Copyright: {\textcopyright} 2002-2012 IEEE.",

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N2 - We propose a new design for covered source-channel tunnel field-effect transistors (CSC-TFETs) with trench gate structures. The I-V characteristics, on/off current ratio, subthreshold swing, and band-to-band tunneling rate are analyzed using a commercial device simulator. Our proposed CSC-TFETs exhibit an on/off current ratio of approximately 1010, an on-current of approximately 10-5 A/μm at room temperature, and a subthreshold swing of less than 40 mV/decade. In addition, the on-current of the CSC-TFETs is ∼233 times that of conventional TFETs, demonstrating that the switching characteristics are superior to those of other silicon-based TFETs. Moreover, a CSC-TFET inverter is characterized by SPICE calibration and provides a high frequency of approximately 1 GHz at a supply voltage of 1.0 V.

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Covered source-channel tunnel field-effect transistors with trench gate structures

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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