Abstract
In this paper, an embedded SRAM architecture of Video application is proposed to reduce the power consumption. By analyzing the general read and write access patterns, the embedded memory is customized to reduce power consumption while achieving general FIFO operations. Some of the signal activations and the Pseudo-read operations are removed in FIFO. According to the simulation results with 65nm CMOS process, the proposed embedded memory for line buffer achieves 17.62% power savings with 3.72% overhead compared to the conventional embedded SRAM approaches.
Original language | English |
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Title of host publication | ISOCC 2016 - International SoC Design Conference |
Subtitle of host publication | Smart SoC for Intelligent Things |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 79-80 |
Number of pages | 2 |
ISBN (Electronic) | 9781467393089 |
DOIs | |
Publication status | Published - 2016 Dec 27 |
Event | 13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26 |
Publication series
Name | ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things |
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Other
Other | 13th International SoC Design Conference, ISOCC 2016 |
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Country/Territory | Korea, Republic of |
City | Jeju |
Period | 16/10/23 → 16/10/26 |
Bibliographical note
Publisher Copyright:© 2016 IEEE.
Keywords
- Embedded memory
- Line buffer
- Low power operation
- Multimedia
- SRAM
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Instrumentation