Conventional data bus inversion (DBI) AC encoding reduces the number of data transitions between current data and previous data by inverting current data. However, if a serializer or a de-serializer (SERDES) is located in the middle of data bus, the DBI applied data correlation is disrupted and DBI AC encoding cannot reduce the number of data transitions any more. In this paper, we present a novel DBI encoding that effectively reduces the number of transitions on the SERDES containg data bus. The proposed scheme determines the inversion status of current data in consideration of previous data both before and after SERDES. As a result, whereas the conventional DBI AC encoding reduces the number of data transitions on entire SERDES-containing data bus by 2.8824%, the proposed encoding scheme achieves 8.3670% of reduction rate.
|Title of host publication||Proceedings - International SoC Design Conference 2022, ISOCC 2022|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2022|
|Event||19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of|
Duration: 2022 Oct 19 → 2022 Oct 22
|Name||Proceedings - International SoC Design Conference 2022, ISOCC 2022|
|Conference||19th International System-on-Chip Design Conference, ISOCC 2022|
|Country/Territory||Korea, Republic of|
|Period||22/10/19 → 22/10/22|
Bibliographical noteFunding Information:
(a) (b) Fig. 1. Differences in data sequences between after and before SERDES and Encoding scheme (a) Conventional SRAM column structure (b) Proposed Bit-Line Decoupled SRAM column structure This work was supported by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820).
© 2022 IEEE.
- Data Bus Inversion AC
- Data Transition Reduction
ASJC Scopus subject areas
- Artificial Intelligence
- Computer Science Applications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality