Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus

Seongyoon Kang; Jongsun Park

doi:10.1109/ISOCC56007.2022.10031583

Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus

Seongyoon Kang, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Conventional data bus inversion (DBI) AC encoding reduces the number of data transitions between current data and previous data by inverting current data. However, if a serializer or a de-serializer (SERDES) is located in the middle of data bus, the DBI applied data correlation is disrupted and DBI AC encoding cannot reduce the number of data transitions any more. In this paper, we present a novel DBI encoding that effectively reduces the number of transitions on the SERDES containg data bus. The proposed scheme determines the inversion status of current data in consideration of previous data both before and after SERDES. As a result, whereas the conventional DBI AC encoding reduces the number of data transitions on entire SERDES-containing data bus by 2.8824%, the proposed encoding scheme achieves 8.3670% of reduction rate.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2022, ISOCC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	103-104
Number of pages	2
ISBN (Electronic)	9781665459716
DOIs	https://doi.org/10.1109/ISOCC56007.2022.10031583
Publication status	Published - 2022
Event	19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of Duration: 2022 Oct 19 → 2022 Oct 22

Publication series

Name	Proceedings - International SoC Design Conference 2022, ISOCC 2022

Conference

Conference	19th International System-on-Chip Design Conference, ISOCC 2022
Country/Territory	Korea, Republic of
City	Gangneung-si
Period	22/10/19 → 22/10/22

Bibliographical note

Funding Information:
(a) (b) Fig. 1. Differences in data sequences between after and before SERDES and Encoding scheme (a) Conventional SRAM column structure (b) Proposed Bit-Line Decoupled SRAM column structure This work was supported by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820).

Publisher Copyright:
© 2022 IEEE.

Keywords

Data Bus Inversion AC
Data Transition Reduction
De-serializer
Serializer

ASJC Scopus subject areas

Artificial Intelligence
Computer Science Applications
Hardware and Architecture
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ISOCC56007.2022.10031583

Cite this

Kang, S., & Park, J. (2022). Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus. In Proceedings - International SoC Design Conference 2022, ISOCC 2022 (pp. 103-104). (Proceedings - International SoC Design Conference 2022, ISOCC 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC56007.2022.10031583

Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus. / Kang, Seongyoon; Park, Jongsun.
Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 103-104 (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kang, S & Park, J 2022, Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus. in Proceedings - International SoC Design Conference 2022, ISOCC 2022. Proceedings - International SoC Design Conference 2022, ISOCC 2022, Institute of Electrical and Electronics Engineers Inc., pp. 103-104, 19th International System-on-Chip Design Conference, ISOCC 2022, Gangneung-si, Korea, Republic of, 22/10/19. https://doi.org/10.1109/ISOCC56007.2022.10031583

@inproceedings{dcf8c0127ca24ce8b4eeda15e895373b,

title = "Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus",

abstract = "Conventional data bus inversion (DBI) AC encoding reduces the number of data transitions between current data and previous data by inverting current data. However, if a serializer or a de-serializer (SERDES) is located in the middle of data bus, the DBI applied data correlation is disrupted and DBI AC encoding cannot reduce the number of data transitions any more. In this paper, we present a novel DBI encoding that effectively reduces the number of transitions on the SERDES containg data bus. The proposed scheme determines the inversion status of current data in consideration of previous data both before and after SERDES. As a result, whereas the conventional DBI AC encoding reduces the number of data transitions on entire SERDES-containing data bus by 2.8824%, the proposed encoding scheme achieves 8.3670% of reduction rate.",

keywords = "Data Bus Inversion AC, Data Transition Reduction, De-serializer, Serializer",

author = "Seongyoon Kang and Jongsun Park",

note = "Funding Information: (a) (b) Fig. 1. Differences in data sequences between after and before SERDES and Encoding scheme (a) Conventional SRAM column structure (b) Proposed Bit-Line Decoupled SRAM column structure This work was supported by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820). Publisher Copyright: {\textcopyright} 2022 IEEE.; 19th International System-on-Chip Design Conference, ISOCC 2022 ; Conference date: 19-10-2022 Through 22-10-2022",

year = "2022",

doi = "10.1109/ISOCC56007.2022.10031583",

language = "English",

series = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "103--104",

booktitle = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

}

TY - GEN

T1 - Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus

AU - Kang, Seongyoon

AU - Park, Jongsun

N1 - Funding Information: (a) (b) Fig. 1. Differences in data sequences between after and before SERDES and Encoding scheme (a) Conventional SRAM column structure (b) Proposed Bit-Line Decoupled SRAM column structure This work was supported by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820). Publisher Copyright: © 2022 IEEE.

PY - 2022

Y1 - 2022

N2 - Conventional data bus inversion (DBI) AC encoding reduces the number of data transitions between current data and previous data by inverting current data. However, if a serializer or a de-serializer (SERDES) is located in the middle of data bus, the DBI applied data correlation is disrupted and DBI AC encoding cannot reduce the number of data transitions any more. In this paper, we present a novel DBI encoding that effectively reduces the number of transitions on the SERDES containg data bus. The proposed scheme determines the inversion status of current data in consideration of previous data both before and after SERDES. As a result, whereas the conventional DBI AC encoding reduces the number of data transitions on entire SERDES-containing data bus by 2.8824%, the proposed encoding scheme achieves 8.3670% of reduction rate.

AB - Conventional data bus inversion (DBI) AC encoding reduces the number of data transitions between current data and previous data by inverting current data. However, if a serializer or a de-serializer (SERDES) is located in the middle of data bus, the DBI applied data correlation is disrupted and DBI AC encoding cannot reduce the number of data transitions any more. In this paper, we present a novel DBI encoding that effectively reduces the number of transitions on the SERDES containg data bus. The proposed scheme determines the inversion status of current data in consideration of previous data both before and after SERDES. As a result, whereas the conventional DBI AC encoding reduces the number of data transitions on entire SERDES-containing data bus by 2.8824%, the proposed encoding scheme achieves 8.3670% of reduction rate.

KW - Data Bus Inversion AC

KW - Data Transition Reduction

KW - De-serializer

KW - Serializer

UR - http://www.scopus.com/inward/record.url?scp=85148471899&partnerID=8YFLogxK

U2 - 10.1109/ISOCC56007.2022.10031583

DO - 10.1109/ISOCC56007.2022.10031583

M3 - Conference contribution

AN - SCOPUS:85148471899

T3 - Proceedings - International SoC Design Conference 2022, ISOCC 2022

SP - 103

EP - 104

BT - Proceedings - International SoC Design Conference 2022, ISOCC 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 19th International System-on-Chip Design Conference, ISOCC 2022

Y2 - 19 October 2022 through 22 October 2022

ER -

Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this