Abstract
In this paper, we present a new discrete cosine transform (DCT) processor architecture using computation sharing multiplication (CSHM). We introduce a computation sharing multiplier based DCT architecture to achieve image quality and hardware complexity trade-off and analyze the performance. Comparison of the performance, area and power consumption with a DA (distributed arithmetic) based DCT architecture is performed. The result shows that the proposed architecture improves power consumption by 14% and area by 41% with acceptable image quality degradation.
Original language | English |
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Title of host publication | ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings |
Editors | A. S. Korotkov |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 162-165 |
Number of pages | 4 |
ISBN (Electronic) | 5742202601, 9785742202608 |
DOIs | |
Publication status | Published - 2002 |
Externally published | Yes |
Event | 1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002 - St.Petersburg, Russian Federation Duration: 2002 Jun 26 → 2002 Jun 28 |
Publication series
Name | ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings |
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Volume | 2002-June |
Other
Other | 1st IEEE International Conference on Circuits and Systems for Communications, ICCSC 2002 |
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Country/Territory | Russian Federation |
City | St.Petersburg |
Period | 02/6/26 → 02/6/28 |
Bibliographical note
Publisher Copyright:© 2002 St. Petersburg State Poly Univ.
ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering