This study demonstrates an optimal design method for the channel length in a p +-i-p-n + structure of feedback field-effect transistors (FBFETs) for next-generation memory devices. We demonstrate the dependence of latch-up and threshold voltages on the channel length in single-gated FBFETs with silicon channels consisting of gated and non-gated regions. The operation principle of the latch-up phenomena related to the channel length using an equivalent circuit in an FBFET has been described. The abrupt increase in the drain current of the single-gated FBFETs at the latch-up (threshold) voltage in the sweep of the drain (gate) voltage was analyzed with current gains in an equivalent circuit. The current gain depends on the gated and non-gated channel lengths; thereby, the latch-up and threshold voltages too depend on the gated and non-gated channel lengths. The dependences of the latch-up and threshold voltages on the non-gated channel length were found to be 3.62 times and 1.68 times higher than that on the gated channel length, respectively.
Bibliographical noteFunding Information:
This research was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT) (2020R1A2C3004538) and the Brain Korea 21 Plus Project in 2022.
© 2022 IOP Publishing Ltd.
- channel length variation
- current gain
- feedback field-effect transistors
- latch-up mechanism
- latch-up voltage
- threshold voltage
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry