Design and Implementation of Display Stream Compression Decoder with Line Buffer Optimization

In recent years, new emerging display-based consumer products, such as augmented and virtual reality headsets and automotive video systems have required higher communication bandwidth due to higher bits per pixel and refresh rates. Thus, many video compression techniques have been actively studied to support the bandwidth in a limited communication environment, and the video electronics standard association (VESA) has standardized a display stream compression (DSC) that provides visually lossless video quality while preserving low power consumption and implementation cost. In this paper, we describe the detailed design of the DSC decoder and optimize a line buffer size that occupies most of the decoder's resources in terms of power and area consumption. So our optimization method can save many resources used by the DSC decoder. The proposed decoder was functionally verified on an FPGA-based platform and synthesized with a 65 nm standard cell library. The performance analysis showed that the optimized decoder used only 62 mW for decoding per frame of FHD video by reducing power consumption by 37.0% and area by 39.9% than the original design; thus, our technology would become an attractive solution for developers of the emerging consumer products.