Abstract
Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (a) a high work function of metal gate and (b) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator's oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.
| Original language | English |
|---|---|
| Article number | 035019 |
| Journal | Semiconductor Science and Technology |
| Volume | 37 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 2022 Mar |
Bibliographical note
Publisher Copyright:© 2022 IOP Publishing Ltd.
Keywords
- CMOS inverter
- complementary FET (CFET)
- junctionless (JL) FET
- junctionless accumulation mode (JAM) FET
- metal ferroelectric insulator semiconductor (MFIS)
- negative capacitance (NC)
- self-heating effect (SHE)
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry