Abstract
Highly scaled (22 nm-node) capacitorless single-transistor dynamic random access memory (DRAM) cell design is investigated via technology computer-aided design (TCAD) simulations. It is found that the gate-sidewall spacer width and operating voltages can be adjusted to reduce bandto- band tunneling (BTBT) and thereby increase data retention time for bipolar junction transistor (BJT)-based operation. Read current variations due to random dopant fluctuations (RDF) are investigated via three-dimensional Kinetic Monte Carlo (KMC) simulations. It is found that BJT-based operation is more robust to RDF effects than metal-oxide-semiconductor field-effect transistor (MOSFET)-based operation.
| Original language | English |
|---|---|
| Article number | 02BD02 |
| Journal | Japanese journal of applied physics |
| Volume | 51 |
| Issue number | 2 PART 2 |
| DOIs | |
| Publication status | Published - 2012 Feb |
| Externally published | Yes |
ASJC Scopus subject areas
- General Engineering
- General Physics and Astronomy