Design optimization of back-gated thin-body silicon-on-insulator capacitorless dynamic random access memory cell

  • Min Hee Cho*
  • , Changhwan Shin
  • , Tsu Jae King Liu
  • *Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

Highly scaled (22 nm-node) capacitorless single-transistor dynamic random access memory (DRAM) cell design is investigated via technology computer-aided design (TCAD) simulations. It is found that the gate-sidewall spacer width and operating voltages can be adjusted to reduce bandto- band tunneling (BTBT) and thereby increase data retention time for bipolar junction transistor (BJT)-based operation. Read current variations due to random dopant fluctuations (RDF) are investigated via three-dimensional Kinetic Monte Carlo (KMC) simulations. It is found that BJT-based operation is more robust to RDF effects than metal-oxide-semiconductor field-effect transistor (MOSFET)-based operation.

Original languageEnglish
Article number02BD02
JournalJapanese journal of applied physics
Volume51
Issue number2 PART 2
DOIs
Publication statusPublished - 2012 Feb
Externally publishedYes

ASJC Scopus subject areas

  • General Engineering
  • General Physics and Astronomy

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