Device Design Guidelines of 3-nm Node Complementary FET (CFET) in Perspective of Electrothermal Characteristics

Seung Geun Jung, Dongwon Jang, Seong Ji Min, Euyjin Park, Hyun Yong Yu

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

For the first time, device design guidelines for a 3-nm node complementary field-effect transistor (CFET), which vertically stacks n-type and p-type nanosheet MOSFETs with a shared gate, are investigated using calibrated 3-D technology computer-aided design (TCAD). Here, the optimal device dimensions of the CFETs for better inverter performance and thermal characteristics are studied. The electrothermal performance are investigated for various vertical dimension parameters of CFET, such as the number of stacked channels, vertical distance between nanosheet channels (Dnsh), distance of n/pMOS separation (Dn/p), and channel thicknesses (Tnsh). The results show that, unlike conventional CMOS, the reduction of Dnsh and Dn/p of CFET can effectively improve inverter performance without severe thermal degradation, although other dimensional parameters trigger a severe trade-off between different electrothermal parameters. The reduction of Dnsh and Dn/p decreases Ceff with a lower metal via the height and gate fringing effect. However, the reduction in Dnsh and Dn/p does not change Reff; therefore, both the operation frequency ( $f$ ) and power-product delay (PDP) can be improved. In the case of thermal characteristics, the reduction of Dnsh and Dn/p slightly increases both Tmax and Rth because of thermal coupling but is negligible. Therefore, the reduction of Dnsh and Dn/p will be a key technique for the development of sub-3-nm CFET.

Original languageEnglish
Pages (from-to)41112-41118
Number of pages7
JournalIEEE Access
Volume10
DOIs
Publication statusPublished - 2022

Bibliographical note

Funding Information:
This work was supported by Samsung Electronics Company, Ltd., under Grant IO210221-08433-01

Publisher Copyright:
© 2013 IEEE.

Keywords

  • 3-nm technology node
  • Complementary FET (CFET)
  • nanosheet FET (NSHFET)
  • technology computer-aided design (TCAD)

ASJC Scopus subject areas

  • General Computer Science
  • General Materials Science
  • General Engineering

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