Device-design optimization of ferroelectric-gated vertical tunnel field-effect transistor to suppress ambipolar current

Device-design optimization of a ferroelectric-gated vertical tunnel field-effect transistor (TFET) with a germanium source is performed using a technology computer-aided design simulation tool. In order to improve the device performance as well as to suppress the ambipolar current, the vertical length of the ferroelectric layer in the gate stack of the TFET is engineered. When the channel region is partially controlled with the ferroelectric layer, the device performance such as the on-state drive current and subthreshold swing (SS) can be improved (e.g. ION ∼ 3.08 10-4 A/μm, ION/IOFF ∼ 3.28 1010, and a minimum SS of 22 mV/decade at 300 K). Moreover, the ambipolar current (Iamb ∼ 21.6 pA/μm) is comparable to or even better than that of the conventional TFET.