This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduces power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full swing of internal nodes. Also, the power consumption of the proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces E × D by 45.5% over ep-SFF. The simulations were performed in a 0.13 um CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Applied Mathematics