Differential Pass Transistor Pulsed Latch

Mooyoung Kim; Inhwa Jung; Youngho Kwak; Sunghoon Ahn; Chulwoo Kim

Differential Pass Transistor Pulsed Latch

Mooyoung Kim, Inhwa Jung, Youngho Kwak, Sunghoon Ahn, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ExD by 42.1% over modified-SAFF. The simulations were performed in a 0.13um CMOS technology at 1.2V supply voltage with 1.25GHz clock frequency.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, 2005 SOCC
Editors	D. Ha, R. Krishnamurthy, S. Kim, A. Marshall
Pages	297-300
Number of pages	4
Publication status	Published - 2005
Event	2005 IEEE International SOC Conference - Herndon, VA, United States Duration: 2005 Sept 25 → 2005 Sept 28

Publication series

Name	Proceedings - IEEE International SOC Conference

Other

Other	2005 IEEE International SOC Conference
Country/Territory	United States
City	Herndon, VA
Period	05/9/25 → 05/9/28

ASJC Scopus subject areas

General Engineering

Cite this

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title = "Differential Pass Transistor Pulsed Latch",

abstract = "This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ExD by 42.1% over modified-SAFF. The simulations were performed in a 0.13um CMOS technology at 1.2V supply voltage with 1.25GHz clock frequency.",

author = "Mooyoung Kim and Inhwa Jung and Youngho Kwak and Sunghoon Ahn and Chulwoo Kim",

year = "2005",

language = "English",

isbn = "0780392647",

series = "Proceedings - IEEE International SOC Conference",

pages = "297--300",

editor = "D. Ha and R. Krishnamurthy and S. Kim and A. Marshall",

booktitle = "Proceedings - IEEE International SOC Conference, 2005 SOCC",

note = "2005 IEEE International SOC Conference ; Conference date: 25-09-2005 Through 28-09-2005",

}

TY - GEN

T1 - Differential Pass Transistor Pulsed Latch

AU - Kim, Mooyoung

AU - Jung, Inhwa

AU - Kwak, Youngho

AU - Ahn, Sunghoon

AU - Kim, Chulwoo

PY - 2005

Y1 - 2005

N2 - This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ExD by 42.1% over modified-SAFF. The simulations were performed in a 0.13um CMOS technology at 1.2V supply voltage with 1.25GHz clock frequency.

AB - This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces ExD by 42.1% over modified-SAFF. The simulations were performed in a 0.13um CMOS technology at 1.2V supply voltage with 1.25GHz clock frequency.

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M3 - Conference contribution

AN - SCOPUS:30844470671

SN - 0780392647

T3 - Proceedings - IEEE International SOC Conference

SP - 297

EP - 300

BT - Proceedings - IEEE International SOC Conference, 2005 SOCC

A2 - Ha, D.

A2 - Krishnamurthy, R.

A2 - Kim, S.

A2 - Marshall, A.

T2 - 2005 IEEE International SOC Conference

Y2 - 25 September 2005 through 28 September 2005

ER -

Differential Pass Transistor Pulsed Latch

Abstract

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