TY - GEN
T1 - Digital signal processing in bio-implantable systems
T2 - 2nd Asia Symposium on Quality Electronic Design, ASQED 2010
AU - Narasimhan, Seetharam
AU - Park, Jongsun
AU - Bhunia, Swarup
PY - 2010
Y1 - 2010
N2 - Implantable systems that monitor biological signals require increasingly complex digital signal processing (DSP) electronics for real-time in-situ analysis and compression of the recorded signals. While it is well-known that such signal processing hardware needs to be implemented under tight area and power constraints for small footprint and increased battery-life, new design requirements emerge with their increasing complexity. Use of nanoscale technology shows tremendous benefits in implementing these advanced circuits due to dramatic improvement in integration density and power dissipation per operation. However, it also brings in new challenges such as reliability and high leakage power. Besides, programmability of the device and security of the recorded information are desirable features, which need to be considered during the design of such systems. Programmability is important to adapt to individual subjects as well as to the temporal fluctuations in subject condition. On the other hand, information security is rapidly becoming an important design parameter since the recorded signal often needs to be transmitted outside the body through wireless channels. In this paper, we analyze the emerging issues associated with the design of the DSP unit in an implantable system. We note that conventional design solutions may not be attractive for such systems. However, novel algorithm-architecture-circuit co-design solutions, which leverage on the nature of the signal processing algorithms can be effective to realize ultra low-power, robust, programmable and secure hardware for on-chip realtime signal processing in implantable systems.
AB - Implantable systems that monitor biological signals require increasingly complex digital signal processing (DSP) electronics for real-time in-situ analysis and compression of the recorded signals. While it is well-known that such signal processing hardware needs to be implemented under tight area and power constraints for small footprint and increased battery-life, new design requirements emerge with their increasing complexity. Use of nanoscale technology shows tremendous benefits in implementing these advanced circuits due to dramatic improvement in integration density and power dissipation per operation. However, it also brings in new challenges such as reliability and high leakage power. Besides, programmability of the device and security of the recorded information are desirable features, which need to be considered during the design of such systems. Programmability is important to adapt to individual subjects as well as to the temporal fluctuations in subject condition. On the other hand, information security is rapidly becoming an important design parameter since the recorded signal often needs to be transmitted outside the body through wireless channels. In this paper, we analyze the emerging issues associated with the design of the DSP unit in an implantable system. We note that conventional design solutions may not be attractive for such systems. However, novel algorithm-architecture-circuit co-design solutions, which leverage on the nature of the signal processing algorithms can be effective to realize ultra low-power, robust, programmable and secure hardware for on-chip realtime signal processing in implantable systems.
KW - Bio-implantable systems
KW - Digital signal processing
KW - Neural interface
KW - Ultralow power design
UR - http://www.scopus.com/inward/record.url?scp=77956501574&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77956501574&partnerID=8YFLogxK
U2 - 10.1109/ASQED.2010.5548247
DO - 10.1109/ASQED.2010.5548247
M3 - Conference contribution
AN - SCOPUS:77956501574
SN - 9781424478088
T3 - Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010
SP - 223
EP - 229
BT - Proceedings of the 2nd Asia Symposium on Quality Electronic Design, ASQED 2010
Y2 - 3 August 2010 through 4 August 2010
ER -