DLL-based 4-phase duty-cycle and phase correction circuit for high frequency clock tree

Keyphrases

• Delay-locked Loop 100%
• Duty Cycle 100%
• Duty Cycle Correction 100%
• Correction Circuit 100%
• Clock Tree 100%
• 4-phase 100%
• Phase Correction 100%
• Delay Line 40%
• Phase Difference 20%
• Rising Edge 20%
• 4-point 20%
• Clock Generator 20%
• Power Dissipation 20%
• Clock Generation 20%
• Timing Margin 20%
• 65nm CMOS 20%
• Clock Distribution 20%
• Phase Clock 20%
• Double Data Rate 20%
• Duty-cycle Error 20%
• High-speed Transmission 20%
• SR Latch 20%
• Distribution Circuit 20%
• Double Sampling 20%

Engineering

• Locked Loop 100%
• Duty Cycle 100%
• Electric Delay Lines 25%
• Simulation Result 12%
• Energy Dissipation 12%
• Rising Edge 12%
• Output Phase 12%
• Phase Difference 12%
• Speed Data 12%
• Double Data Rate Memory 12%
• Maximum Duty Cycle 12%