Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency

Jinil Chung; Jongsun Park; Swaroop Ghosh

doi:10.1145/2934583.2934602

Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency

Jinil Chung
, Jongsun Park
, Swaroop Ghosh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Citations (Scopus)

Abstract

In the hardware implementation of deep learning algorithms such as Convolutional Neural Networks (CNNs), vector-vector multiplications and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a Domain Wall Memory (DWM) based design of CNN convolutional layer. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design a low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and power cost of the input registers for aligning inputs. Contrary to the conventional implementation using Memristor-Based Crossbar (MBC), the bit-width of the proposed CNN convolutional layer is extendable for high resolution classifications and training. Simulation results using 65 nm CMOS process show that the proposed design archives 34% of energy savings compared to the conventional MBC based design approach.

Original language	English
Title of host publication	ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	332-337
Number of pages	6
ISBN (Electronic)	9781450341851
DOIs	https://doi.org/10.1145/2934583.2934602
Publication status	Published - 2016 Aug 8
Event	21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016 - San Francisco, United States Duration: 2016 Aug 8 → 2016 Aug 10

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016
Country/Territory	United States
City	San Francisco
Period	16/8/8 → 16/8/10

Bibliographical note

Publisher Copyright:
© 2016 ACM.

Keywords

Convolutional Neural Networks
Domain Wall Memory
Embedded Memory

ASJC Scopus subject areas

General Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1145/2934583.2934602

Cite this

Chung, J., Park, J., & Ghosh, S. (2016). Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency. In ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design (pp. 332-337). (Proceedings of the International Symposium on Low Power Electronics and Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2934583.2934602

Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency. / Chung, Jinil; Park, Jongsun; Ghosh, Swaroop.
ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2016. p. 332-337 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chung, J, Park, J & Ghosh, S 2016, Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency. in ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, Institute of Electrical and Electronics Engineers Inc., pp. 332-337, 21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016, San Francisco, United States, 16/8/8. https://doi.org/10.1145/2934583.2934602

Chung J, Park J, Ghosh S. Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency. In ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc. 2016. p. 332-337. (Proceedings of the International Symposium on Low Power Electronics and Design). doi: 10.1145/2934583.2934602

Chung, Jinil ; Park, Jongsun ; Ghosh, Swaroop. / Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency. ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 332-337 (Proceedings of the International Symposium on Low Power Electronics and Design).

@inproceedings{14cbc0c72cd24bbcba25dbc12b16b5d1,

title = "Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency",

abstract = "In the hardware implementation of deep learning algorithms such as Convolutional Neural Networks (CNNs), vector-vector multiplications and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a Domain Wall Memory (DWM) based design of CNN convolutional layer. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design a low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and power cost of the input registers for aligning inputs. Contrary to the conventional implementation using Memristor-Based Crossbar (MBC), the bit-width of the proposed CNN convolutional layer is extendable for high resolution classifications and training. Simulation results using 65 nm CMOS process show that the proposed design archives 34\% of energy savings compared to the conventional MBC based design approach.",

keywords = "Convolutional Neural Networks, Domain Wall Memory, Embedded Memory",

author = "Jinil Chung and Jongsun Park and Swaroop Ghosh",

note = "Publisher Copyright: {\textcopyright} 2016 ACM.; 21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016 ; Conference date: 08-08-2016 Through 10-08-2016",

year = "2016",

month = aug,

day = "8",

doi = "10.1145/2934583.2934602",

language = "English",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "332--337",

booktitle = "ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design",

}

TY - GEN

T1 - Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency

AU - Chung, Jinil

AU - Park, Jongsun

AU - Ghosh, Swaroop

PY - 2016/8/8

Y1 - 2016/8/8

N2 - In the hardware implementation of deep learning algorithms such as Convolutional Neural Networks (CNNs), vector-vector multiplications and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a Domain Wall Memory (DWM) based design of CNN convolutional layer. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design a low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and power cost of the input registers for aligning inputs. Contrary to the conventional implementation using Memristor-Based Crossbar (MBC), the bit-width of the proposed CNN convolutional layer is extendable for high resolution classifications and training. Simulation results using 65 nm CMOS process show that the proposed design archives 34% of energy savings compared to the conventional MBC based design approach.

AB - In the hardware implementation of deep learning algorithms such as Convolutional Neural Networks (CNNs), vector-vector multiplications and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a Domain Wall Memory (DWM) based design of CNN convolutional layer. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design a low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and power cost of the input registers for aligning inputs. Contrary to the conventional implementation using Memristor-Based Crossbar (MBC), the bit-width of the proposed CNN convolutional layer is extendable for high resolution classifications and training. Simulation results using 65 nm CMOS process show that the proposed design archives 34% of energy savings compared to the conventional MBC based design approach.

KW - Convolutional Neural Networks

KW - Domain Wall Memory

KW - Embedded Memory

UR - https://www.scopus.com/pages/publications/84988007983

U2 - 10.1145/2934583.2934602

DO - 10.1145/2934583.2934602

M3 - Conference contribution

AN - SCOPUS:84988007983

T3 - Proceedings of the International Symposium on Low Power Electronics and Design

SP - 332

EP - 337

BT - ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016

Y2 - 8 August 2016 through 10 August 2016

ER -

Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency

Abstract

Publication series

Other

Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this