Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers

Jinil Chung; Woong Choi; Jongsun Park; Swaroop Ghosh

doi:10.1109/ACCESS.2020.2968081

Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers

Jinil Chung, Woong Choi, Jongsun Park, Swaroop Ghosh

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

In the hardware implementation of deep learning algorithms such as, convolutional neural networks (CNNs) and binarized neural networks (BNNs), multiple dot products and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a domain wall memory (DWM) based design of CNN and BNN convolutional layers. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and energy cost of DWM-based design for filter sliding. Simulation results with 65 nm CMOS process show 45% and 43% of energy savings compared to the conventional CNN and BNN design approach, respectively.

Original language	English
Article number	8963965
Pages (from-to)	19783-19798
Number of pages	16
Journal	IEEE Access
Volume	8
DOIs	https://doi.org/10.1109/ACCESS.2020.2968081
Publication status	Published - 2020

Bibliographical note

Funding Information:
This work was supported in part by the National Research Foundation of Korea under Grant NRF-2015M3D1A1070465, in part by the Ministry of Science (MSIT) and ICT, South Korea, under the Information Technology Research Center (ITRC) under Grant IITP-2020-2018-0-01433) supervised by the Institute for Information & Communications Technology Promotion (IITP), and in part by the Industrial Strategic Technology Development Program under Grant 10077445, and in part by the Development of SoC Technology based on Spiking Neural Cell for smart mobile and IoT Devices funded by the Ministry of Trade, Industry and Energy (MOTIE, Korea).

Publisher Copyright:
© 2013 IEEE.

Keywords

Binarized neural network
convolutional neural network
deep neural network
domain wall memory

ASJC Scopus subject areas

General Computer Science
General Materials Science
General Engineering

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10.1109/ACCESS.2020.2968081

Cite this

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title = "Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers",

abstract = "In the hardware implementation of deep learning algorithms such as, convolutional neural networks (CNNs) and binarized neural networks (BNNs), multiple dot products and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a domain wall memory (DWM) based design of CNN and BNN convolutional layers. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and energy cost of DWM-based design for filter sliding. Simulation results with 65 nm CMOS process show 45% and 43% of energy savings compared to the conventional CNN and BNN design approach, respectively.",

keywords = "Binarized neural network, convolutional neural network, deep neural network, domain wall memory",

author = "Jinil Chung and Woong Choi and Jongsun Park and Swaroop Ghosh",

note = "Funding Information: This work was supported in part by the National Research Foundation of Korea under Grant NRF-2015M3D1A1070465, in part by the Ministry of Science (MSIT) and ICT, South Korea, under the Information Technology Research Center (ITRC) under Grant IITP-2020-2018-0-01433) supervised by the Institute for Information & Communications Technology Promotion (IITP), and in part by the Industrial Strategic Technology Development Program under Grant 10077445, and in part by the Development of SoC Technology based on Spiking Neural Cell for smart mobile and IoT Devices funded by the Ministry of Trade, Industry and Energy (MOTIE, Korea). Publisher Copyright: {\textcopyright} 2013 IEEE.",

year = "2020",

doi = "10.1109/ACCESS.2020.2968081",

language = "English",

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AU - Chung, Jinil

AU - Choi, Woong

AU - Park, Jongsun

AU - Ghosh, Swaroop

N1 - Funding Information: This work was supported in part by the National Research Foundation of Korea under Grant NRF-2015M3D1A1070465, in part by the Ministry of Science (MSIT) and ICT, South Korea, under the Information Technology Research Center (ITRC) under Grant IITP-2020-2018-0-01433) supervised by the Institute for Information & Communications Technology Promotion (IITP), and in part by the Industrial Strategic Technology Development Program under Grant 10077445, and in part by the Development of SoC Technology based on Spiking Neural Cell for smart mobile and IoT Devices funded by the Ministry of Trade, Industry and Energy (MOTIE, Korea). Publisher Copyright: © 2013 IEEE.

PY - 2020

Y1 - 2020

N2 - In the hardware implementation of deep learning algorithms such as, convolutional neural networks (CNNs) and binarized neural networks (BNNs), multiple dot products and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a domain wall memory (DWM) based design of CNN and BNN convolutional layers. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and energy cost of DWM-based design for filter sliding. Simulation results with 65 nm CMOS process show 45% and 43% of energy savings compared to the conventional CNN and BNN design approach, respectively.

AB - In the hardware implementation of deep learning algorithms such as, convolutional neural networks (CNNs) and binarized neural networks (BNNs), multiple dot products and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a domain wall memory (DWM) based design of CNN and BNN convolutional layers. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and energy cost of DWM-based design for filter sliding. Simulation results with 65 nm CMOS process show 45% and 43% of energy savings compared to the conventional CNN and BNN design approach, respectively.

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KW - deep neural network

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Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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