Double precharge TSPC for high-speed dual-modulus prescaler

Kwan Yeob Chae, Hoon Jae Ki, In Chul Hwang, Soo Won Kim

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    A double precharge TSPC D-flip-flop (DFF) is proposed and a 3 GHz dual-modulus prescaler using the double precharge TSPC in 0.35 μm CMOS technology is presented in this paper. The double precharge TSPC DFF can reduce setup time compared with the conventional one, so it contributes to enhancing the operating speed of a dual-modulus prescaler. A 128/129 dual-modulus prescaler using the proposed flip-flop shows a maximum operating frequency of 3 GHz with 16 mW power consumption at 3.3 V power supply.

    Original languageEnglish
    Title of host publicationICVC 1999 - 6th International Conference on VLSI and CAD
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages609-612
    Number of pages4
    ISBN (Print)0780357272, 9780780357273
    DOIs
    Publication statusPublished - 1999
    Event6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of
    Duration: 1999 Oct 261999 Oct 27

    Publication series

    NameICVC 1999 - 6th International Conference on VLSI and CAD

    Other

    Other6th International Conference on VLSI and CAD, ICVC 1999
    Country/TerritoryKorea, Republic of
    CitySeoul
    Period99/10/2699/10/27

    Bibliographical note

    Publisher Copyright:
    © 1999 IEEE.

    ASJC Scopus subject areas

    • Computer Graphics and Computer-Aided Design
    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

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