Double precharge TSPC for high-speed dual-modulus prescaler

Kwan Yeob Chae; Hoon Jae Ki; In Chul Hwang; Soo Won Kim

doi:10.1109/ICVC.1999.821014

Double precharge TSPC for high-speed dual-modulus prescaler

Kwan Yeob Chae, Hoon Jae Ki, In Chul Hwang, Soo Won Kim

* Honorary professors

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A double precharge TSPC D-flip-flop (DFF) is proposed and a 3 GHz dual-modulus prescaler using the double precharge TSPC in 0.35 μm CMOS technology is presented in this paper. The double precharge TSPC DFF can reduce setup time compared with the conventional one, so it contributes to enhancing the operating speed of a dual-modulus prescaler. A 128/129 dual-modulus prescaler using the proposed flip-flop shows a maximum operating frequency of 3 GHz with 16 mW power consumption at 3.3 V power supply.

Original language	English
Title of host publication	ICVC 1999 - 6th International Conference on VLSI and CAD
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	609-612
Number of pages	4
ISBN (Print)	0780357272, 9780780357273
DOIs	https://doi.org/10.1109/ICVC.1999.821014
Publication status	Published - 1999
Event	6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of Duration: 1999 Oct 26 → 1999 Oct 27

Publication series

Name	ICVC 1999 - 6th International Conference on VLSI and CAD

Other

Other	6th International Conference on VLSI and CAD, ICVC 1999
Country/Territory	Korea, Republic of
City	Seoul
Period	99/10/26 → 99/10/27

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ICVC.1999.821014

Cite this

Double precharge TSPC for high-speed dual-modulus prescaler. / Chae, Kwan Yeob; Ki, Hoon Jae; Hwang, In Chul et al.
ICVC 1999 - 6th International Conference on VLSI and CAD. Institute of Electrical and Electronics Engineers Inc., 1999. p. 609-612 821014 (ICVC 1999 - 6th International Conference on VLSI and CAD).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chae, KY, Ki, HJ, Hwang, IC & Kim, SW 1999, Double precharge TSPC for high-speed dual-modulus prescaler. in ICVC 1999 - 6th International Conference on VLSI and CAD., 821014, ICVC 1999 - 6th International Conference on VLSI and CAD, Institute of Electrical and Electronics Engineers Inc., pp. 609-612, 6th International Conference on VLSI and CAD, ICVC 1999, Seoul, Korea, Republic of, 99/10/26. https://doi.org/10.1109/ICVC.1999.821014

@inproceedings{f521d09057094f6c8466e401a0c943aa,

title = "Double precharge TSPC for high-speed dual-modulus prescaler",

abstract = "A double precharge TSPC D-flip-flop (DFF) is proposed and a 3 GHz dual-modulus prescaler using the double precharge TSPC in 0.35 μm CMOS technology is presented in this paper. The double precharge TSPC DFF can reduce setup time compared with the conventional one, so it contributes to enhancing the operating speed of a dual-modulus prescaler. A 128/129 dual-modulus prescaler using the proposed flip-flop shows a maximum operating frequency of 3 GHz with 16 mW power consumption at 3.3 V power supply.",

author = "Chae, {Kwan Yeob} and Ki, {Hoon Jae} and Hwang, {In Chul} and Kim, {Soo Won}",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 6th International Conference on VLSI and CAD, ICVC 1999 ; Conference date: 26-10-1999 Through 27-10-1999",

year = "1999",

doi = "10.1109/ICVC.1999.821014",

language = "English",

isbn = "0780357272",

series = "ICVC 1999 - 6th International Conference on VLSI and CAD",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "609--612",

booktitle = "ICVC 1999 - 6th International Conference on VLSI and CAD",

}

TY - GEN

T1 - Double precharge TSPC for high-speed dual-modulus prescaler

AU - Chae, Kwan Yeob

AU - Ki, Hoon Jae

AU - Hwang, In Chul

AU - Kim, Soo Won

PY - 1999

Y1 - 1999

N2 - A double precharge TSPC D-flip-flop (DFF) is proposed and a 3 GHz dual-modulus prescaler using the double precharge TSPC in 0.35 μm CMOS technology is presented in this paper. The double precharge TSPC DFF can reduce setup time compared with the conventional one, so it contributes to enhancing the operating speed of a dual-modulus prescaler. A 128/129 dual-modulus prescaler using the proposed flip-flop shows a maximum operating frequency of 3 GHz with 16 mW power consumption at 3.3 V power supply.

AB - A double precharge TSPC D-flip-flop (DFF) is proposed and a 3 GHz dual-modulus prescaler using the double precharge TSPC in 0.35 μm CMOS technology is presented in this paper. The double precharge TSPC DFF can reduce setup time compared with the conventional one, so it contributes to enhancing the operating speed of a dual-modulus prescaler. A 128/129 dual-modulus prescaler using the proposed flip-flop shows a maximum operating frequency of 3 GHz with 16 mW power consumption at 3.3 V power supply.

UR - http://www.scopus.com/inward/record.url?scp=14544271235&partnerID=8YFLogxK

U2 - 10.1109/ICVC.1999.821014

DO - 10.1109/ICVC.1999.821014

M3 - Conference contribution

AN - SCOPUS:14544271235

SN - 0780357272

SN - 9780780357273

T3 - ICVC 1999 - 6th International Conference on VLSI and CAD

SP - 609

EP - 612

BT - ICVC 1999 - 6th International Conference on VLSI and CAD

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 6th International Conference on VLSI and CAD, ICVC 1999

Y2 - 26 October 1999 through 27 October 1999

ER -

Double precharge TSPC for high-speed dual-modulus prescaler

Abstract

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