@inproceedings{f521d09057094f6c8466e401a0c943aa,
title = "Double precharge TSPC for high-speed dual-modulus prescaler",
abstract = "A double precharge TSPC D-flip-flop (DFF) is proposed and a 3 GHz dual-modulus prescaler using the double precharge TSPC in 0.35 μm CMOS technology is presented in this paper. The double precharge TSPC DFF can reduce setup time compared with the conventional one, so it contributes to enhancing the operating speed of a dual-modulus prescaler. A 128/129 dual-modulus prescaler using the proposed flip-flop shows a maximum operating frequency of 3 GHz with 16 mW power consumption at 3.3 V power supply.",
author = "Chae, {Kwan Yeob} and Ki, {Hoon Jae} and Hwang, {In Chul} and Kim, {Soo Won}",
note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 6th International Conference on VLSI and CAD, ICVC 1999 ; Conference date: 26-10-1999 Through 27-10-1999",
year = "1999",
doi = "10.1109/ICVC.1999.821014",
language = "English",
isbn = "0780357272",
series = "ICVC 1999 - 6th International Conference on VLSI and CAD",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "609--612",
booktitle = "ICVC 1999 - 6th International Conference on VLSI and CAD",
}