Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

Dae Young Jeon, So Jeong Park, Mireille Mouis, Sylvain Barraud, Gyu Tae Kim, Gérard Ghibaudo

Research output: Contribution to journalArticlepeer-review

31 Citations (Scopus)

Abstract

The electrical behavior of tri-gate Junctionless transistors (JLTs) depending on top-effective width (Wtop-eff) was investigated, experimentally. As decreasing Wtop-eff, the amount of bulk neutral channel is relatively getting smaller than that of surface accumulation channel, whereas the channel sidewall gate effect is reinforced. These cause the shrinkage of the shoulder shape on the gate-to-channel capacitance characteristics (Cgc-Vg), resulting in a noticeable change in the effective mobility (μeff) behavior from that in wide JLT devices, an increase of the threshold voltage (Vth), while the flat-band voltage (Vfb) does not change. 2D numerical simulation results, well consistent to the experimental results, confirm the significant sidewall gate effect in the tri-gate JLT devices with a narrow structure.

Original languageEnglish
Pages (from-to)58-62
Number of pages5
JournalSolid-State Electronics
Volume81
DOIs
Publication statusPublished - 2013

Bibliographical note

Funding Information:
This work was supported by European Union 7th Framework Program project SQWIRE under Grant agreement No. 257111 and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (Converging Research Center Program, 2012K001313 and Global Frontier Research Program, No. 2011-0031638).

Keywords

  • 2D numerical simulation
  • Effective mobility (μ)
  • Effective width
  • Flat-band voltage (V)
  • Junctionless transistors (JLTs)
  • Sidewall gate effect
  • Threshold voltage (V)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Materials Chemistry
  • Electrical and Electronic Engineering

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