Abstract
This paper presents an efficient discrete-time bandpass sigma-delta (∑Δ) modulator and digital in-phase/quadrature (I/Q) demodulator for multistandard wireless applications. The proposed bandpass ∑Δ modulator provides higher speed using advanced switched-capacitor resonators which are faster than the conventional ones. The test chip has been implemented in a 0.18 μm CMOS process and occupied with the active chip area of 0.16 mm2. The power consumption of the fabricated chip is 2.34 mW with a 1.8 V supply voltage. The measured peak signal-to-noise ratios (SNR) are 34 dB for 1.536 MHz (T-DMB), 26 dB for 5 MHz (UMTS), and 20 dB for 10 MHz (WiBro) bandwidths, respectively. This paper also covers the simple and robust digital I/Q demodulator which has been realized using a field programmable gate array (FPGA) for digital signal processing.
Original language | English |
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Pages (from-to) | 25-32 |
Number of pages | 8 |
Journal | IEEE Transactions on Consumer Electronics |
Volume | 54 |
Issue number | 1 |
DOIs | |
Publication status | Published - 2008 Feb |
Bibliographical note
Funding Information:1This work was supported by Samsung Electro-Mechanics Co., Ltd. and Korea University. C. Jeong is with Mobile RF R&D Group, Samsung Electro-Mechanics Co., Ltd., Suwon 443-743, Korea (e-mail: [email protected]). Y. Kim and S. Kim are with the Department of Electronics Engineering, Korea University, Seoul 136-701, Korea (e-mail: [email protected], [email protected]).
Keywords
- Bandpass
- Digital demodulator
- Discretetime
- Sigma-delta modulation
ASJC Scopus subject areas
- Media Technology
- Electrical and Electronic Engineering