Efficient discrete-time bandpass sigma-delta modulator and digital I/Q demodulator for multistandard wireless applications

Chanyong Jeong; Yonghwan Kim; Soowon Kim

doi:10.1109/TCE.2008.4470019

Efficient discrete-time bandpass sigma-delta modulator and digital I/Q demodulator for multistandard wireless applications

Chanyong Jeong, Yonghwan Kim, Soowon Kim

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

This paper presents an efficient discrete-time bandpass sigma-delta (∑Δ) modulator and digital in-phase/quadrature (I/Q) demodulator for multistandard wireless applications. The proposed bandpass ∑Δ modulator provides higher speed using advanced switched-capacitor resonators which are faster than the conventional ones. The test chip has been implemented in a 0.18 μm CMOS process and occupied with the active chip area of 0.16 mm². The power consumption of the fabricated chip is 2.34 mW with a 1.8 V supply voltage. The measured peak signal-to-noise ratios (SNR) are 34 dB for 1.536 MHz (T-DMB), 26 dB for 5 MHz (UMTS), and 20 dB for 10 MHz (WiBro) bandwidths, respectively. This paper also covers the simple and robust digital I/Q demodulator which has been realized using a field programmable gate array (FPGA) for digital signal processing.

Original language	English
Pages (from-to)	25-32
Number of pages	8
Journal	IEEE Transactions on Consumer Electronics
Volume	54
Issue number	1
DOIs	https://doi.org/10.1109/TCE.2008.4470019
Publication status	Published - 2008 Feb

Bibliographical note

Funding Information:
1This work was supported by Samsung Electro-Mechanics Co., Ltd. and Korea University. C. Jeong is with Mobile RF R&D Group, Samsung Electro-Mechanics Co., Ltd., Suwon 443-743, Korea (e-mail: [email protected]). Y. Kim and S. Kim are with the Department of Electronics Engineering, Korea University, Seoul 136-701, Korea (e-mail: [email protected], [email protected]).

Keywords

Bandpass
Digital demodulator
Discretetime
Sigma-delta modulation

ASJC Scopus subject areas

Media Technology
Electrical and Electronic Engineering

Access to Document

10.1109/TCE.2008.4470019

Cite this

@article{a0d11e8f16684a92aeea4fee5c54d5bf,

title = "Efficient discrete-time bandpass sigma-delta modulator and digital I/Q demodulator for multistandard wireless applications",

abstract = "This paper presents an efficient discrete-time bandpass sigma-delta (∑Δ) modulator and digital in-phase/quadrature (I/Q) demodulator for multistandard wireless applications. The proposed bandpass ∑Δ modulator provides higher speed using advanced switched-capacitor resonators which are faster than the conventional ones. The test chip has been implemented in a 0.18 μm CMOS process and occupied with the active chip area of 0.16 mm2. The power consumption of the fabricated chip is 2.34 mW with a 1.8 V supply voltage. The measured peak signal-to-noise ratios (SNR) are 34 dB for 1.536 MHz (T-DMB), 26 dB for 5 MHz (UMTS), and 20 dB for 10 MHz (WiBro) bandwidths, respectively. This paper also covers the simple and robust digital I/Q demodulator which has been realized using a field programmable gate array (FPGA) for digital signal processing.",

keywords = "Bandpass, Digital demodulator, Discretetime, Sigma-delta modulation",

author = "Chanyong Jeong and Yonghwan Kim and Soowon Kim",

note = "Funding Information: 1This work was supported by Samsung Electro-Mechanics Co., Ltd. and Korea University. C. Jeong is with Mobile RF R&D Group, Samsung Electro-Mechanics Co., Ltd., Suwon 443-743, Korea (e-mail: [email protected]). Y. Kim and S. Kim are with the Department of Electronics Engineering, Korea University, Seoul 136-701, Korea (e-mail: [email protected], [email protected]).",

year = "2008",

month = feb,

doi = "10.1109/TCE.2008.4470019",

language = "English",

volume = "54",

pages = "25--32",

journal = "IEEE Transactions on Consumer Electronics",

issn = "0098-3063",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - Efficient discrete-time bandpass sigma-delta modulator and digital I/Q demodulator for multistandard wireless applications

AU - Jeong, Chanyong

AU - Kim, Yonghwan

AU - Kim, Soowon

N1 - Funding Information: 1This work was supported by Samsung Electro-Mechanics Co., Ltd. and Korea University. C. Jeong is with Mobile RF R&D Group, Samsung Electro-Mechanics Co., Ltd., Suwon 443-743, Korea (e-mail: [email protected]). Y. Kim and S. Kim are with the Department of Electronics Engineering, Korea University, Seoul 136-701, Korea (e-mail: [email protected], [email protected]).

PY - 2008/2

Y1 - 2008/2

N2 - This paper presents an efficient discrete-time bandpass sigma-delta (∑Δ) modulator and digital in-phase/quadrature (I/Q) demodulator for multistandard wireless applications. The proposed bandpass ∑Δ modulator provides higher speed using advanced switched-capacitor resonators which are faster than the conventional ones. The test chip has been implemented in a 0.18 μm CMOS process and occupied with the active chip area of 0.16 mm2. The power consumption of the fabricated chip is 2.34 mW with a 1.8 V supply voltage. The measured peak signal-to-noise ratios (SNR) are 34 dB for 1.536 MHz (T-DMB), 26 dB for 5 MHz (UMTS), and 20 dB for 10 MHz (WiBro) bandwidths, respectively. This paper also covers the simple and robust digital I/Q demodulator which has been realized using a field programmable gate array (FPGA) for digital signal processing.

AB - This paper presents an efficient discrete-time bandpass sigma-delta (∑Δ) modulator and digital in-phase/quadrature (I/Q) demodulator for multistandard wireless applications. The proposed bandpass ∑Δ modulator provides higher speed using advanced switched-capacitor resonators which are faster than the conventional ones. The test chip has been implemented in a 0.18 μm CMOS process and occupied with the active chip area of 0.16 mm2. The power consumption of the fabricated chip is 2.34 mW with a 1.8 V supply voltage. The measured peak signal-to-noise ratios (SNR) are 34 dB for 1.536 MHz (T-DMB), 26 dB for 5 MHz (UMTS), and 20 dB for 10 MHz (WiBro) bandwidths, respectively. This paper also covers the simple and robust digital I/Q demodulator which has been realized using a field programmable gate array (FPGA) for digital signal processing.

KW - Bandpass

KW - Digital demodulator

KW - Discretetime

KW - Sigma-delta modulation

UR - http://www.scopus.com/inward/record.url?scp=41649103686&partnerID=8YFLogxK

U2 - 10.1109/TCE.2008.4470019

DO - 10.1109/TCE.2008.4470019

M3 - Article

AN - SCOPUS:41649103686

SN - 0098-3063

VL - 54

SP - 25

EP - 32

JO - IEEE Transactions on Consumer Electronics

JF - IEEE Transactions on Consumer Electronics

IS - 1

ER -

Efficient discrete-time bandpass sigma-delta modulator and digital I/Q demodulator for multistandard wireless applications

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this