Charge trapping is dramatically suppressed in ZnO transparent thin film transistors (TFTs) employing a multilayered gate insulator with Hf O2 layer sandwiched by Al2 O3 layers. In spite of its high dielectric constant, Hf O2 has critical drawbacks including huge charge trap density in interfaces. We suggest and demonstrate an elegant solution to minimize the charge trapping introducing Al2 O3 buffer layers. The operation of Al2 O3 Hf O2 Al2 O3 multilayered gate-insulator structure in the ZnO transparent TFT is evaluated to ensure the voltage difference in the hysteresis loop as low as 0.2 V, and the immunization to the threshold voltage shift induced by repeated sweeps of gate voltage.
Bibliographical noteFunding Information:
This work was supported by the Core Competence Project internally funded from KIST. We thank J.-H. Kwon in Display and Nanosystem Laboratory (Dept. of Electronics and Electrical Engineering, Korea University) for advice and discussion. We also thank Dr. S. H. Lee in our team for characteristics analysis and fruitful discussion.
ASJC Scopus subject areas
- Physics and Astronomy (miscellaneous)