Efficient TSV Fault Detection Scheme for High Bandwidth Memory Using Pattern Analysis

Kwanho Bae; Jongsun Park

doi:10.1109/ISOCC50952.2020.9333115

Efficient TSV Fault Detection Scheme for High Bandwidth Memory Using Pattern Analysis

Kwanho Bae, Jongsun Park

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

For an efficient data transmission between logic die and core die in HBM DRAM, Through-Silicon-Via (TSV) is an essential part that connects stacked memories. TSV is a vertical component which cannot be found in the conventional 2D memory. It plays an important role in improving integration in 3D memory structure. However, due to its temporal variation and technological weakness, error cases occur frequently in TSV. Following this, to increase the reliability of the memory operation, fault detection and correction method for TSV is a new challenge in 3D memory. For the efficient fault correction, fault detection method that classifies hard fault and soft error has been studied. In this paper, a new TSV fault detection method using error pattern analysis will be presented. As a result, the proposed scheme shows higher detection success rate with low area overhead, compared to the conventional scheme.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	19-20
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9333115
Publication status	Published - 2020 Oct 21
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 2020 Oct 21 → 2020 Oct 24

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	20/10/21 → 20/10/24

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

Error-Correction-Code(ECC)
High Bandwidth memory(HBM)
Through-Silicon-Via(TSV)

ASJC Scopus subject areas

Energy Engineering and Power Technology
Electrical and Electronic Engineering
Instrumentation
Artificial Intelligence
Hardware and Architecture

Access to Document

10.1109/ISOCC50952.2020.9333115

Cite this

Bae, K., & Park, J. (2020). Efficient TSV Fault Detection Scheme for High Bandwidth Memory Using Pattern Analysis. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 19-20). Article 9333115 (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9333115

Efficient TSV Fault Detection Scheme for High Bandwidth Memory Using Pattern Analysis. / Bae, Kwanho; Park, Jongsun.
Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 19-20 9333115 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Bae, K & Park, J 2020, Efficient TSV Fault Detection Scheme for High Bandwidth Memory Using Pattern Analysis. in Proceedings - International SoC Design Conference, ISOCC 2020., 9333115, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 19-20, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 20/10/21. https://doi.org/10.1109/ISOCC50952.2020.9333115

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Efficient TSV Fault Detection Scheme for High Bandwidth Memory Using Pattern Analysis

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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