In this study, Si-nanoparticle(NP)/Si-nanowire(NW)-based field-effect transistors (FETs) with a top-gate geometry were fabricated and characterized. In these FETs, Si NPs were embedded as localized trap sites in Al 2O3 top-gate layers coated on Si NW channels. Drain current versus drain voltage (I DS-V DS) and drain current versus gate voltage (I DS-V GS) were measured for the Si NP/Si NW-based FETs to investigate their electrical and memory characteristics. The Si NW channels were depleted at V GS= 9 V, indicating that the devices functioned as p-type depletion-mode FETs. The top-gate Si NW-based FETs decorated with Si NPs show counterclockwise hysteresis loops in the I DS-V GS curves, revealing their significant charge storage effect.
Bibliographical noteFunding Information:
Acknowledgement This work was supported by the Center for Integrated-Nano-Systems (CINS) of the Korea Research Foundation (KRF-2006-005-J03601), the Korea Science and Engineering Foundation (KOSEF) through the National Research Lab. Program (R0A-2005-000-10045-02 (2007)), the Nano R&D Program (M10703000980-07M0300-98010), and ‘‘SystemIC2010’’ project of Korea Ministry of Commerce, Industry and Energy.
ASJC Scopus subject areas
- Materials Science(all)
- Mechanics of Materials
- Mechanical Engineering