Electrical characteristics of Si-nanoparticle/Si-nanowire-based field-effect transistors

Jeongmin Kang; Kihyun Keem; Dong Young Jeong; Miyoung Park; Dongmok Whang; Sangsig Kim

doi:10.1007/s10853-007-2310-6

Electrical characteristics of Si-nanoparticle/Si-nanowire-based field-effect transistors

Jeongmin Kang, Kihyun Keem, Dong Young Jeong, Miyoung Park, Dongmok Whang, Sangsig Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

In this study, Si-nanoparticle(NP)/Si-nanowire(NW)-based field-effect transistors (FETs) with a top-gate geometry were fabricated and characterized. In these FETs, Si NPs were embedded as localized trap sites in Al ₂O₃ top-gate layers coated on Si NW channels. Drain current versus drain voltage (I _DS-V _DS) and drain current versus gate voltage (I _DS-V _GS) were measured for the Si NP/Si NW-based FETs to investigate their electrical and memory characteristics. The Si NW channels were depleted at V _GS= 9 V, indicating that the devices functioned as p-type depletion-mode FETs. The top-gate Si NW-based FETs decorated with Si NPs show counterclockwise hysteresis loops in the I _DS-V _GS curves, revealing their significant charge storage effect.

Original language	English
Pages (from-to)	3424-3428
Number of pages	5
Journal	Journal of Materials Science
Volume	43
Issue number	10
DOIs	https://doi.org/10.1007/s10853-007-2310-6
Publication status	Published - 2008 May

Bibliographical note

Funding Information:
Acknowledgement This work was supported by the Center for Integrated-Nano-Systems (CINS) of the Korea Research Foundation (KRF-2006-005-J03601), the Korea Science and Engineering Foundation (KOSEF) through the National Research Lab. Program (R0A-2005-000-10045-02 (2007)), the Nano R&D Program (M10703000980-07M0300-98010), and ‘‘SystemIC2010’’ project of Korea Ministry of Commerce, Industry and Energy.

ASJC Scopus subject areas

Materials Science(all)
Mechanics of Materials
Mechanical Engineering

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title = "Electrical characteristics of Si-nanoparticle/Si-nanowire-based field-effect transistors",

abstract = "In this study, Si-nanoparticle(NP)/Si-nanowire(NW)-based field-effect transistors (FETs) with a top-gate geometry were fabricated and characterized. In these FETs, Si NPs were embedded as localized trap sites in Al 2O3 top-gate layers coated on Si NW channels. Drain current versus drain voltage (I DS-V DS) and drain current versus gate voltage (I DS-V GS) were measured for the Si NP/Si NW-based FETs to investigate their electrical and memory characteristics. The Si NW channels were depleted at V GS= 9 V, indicating that the devices functioned as p-type depletion-mode FETs. The top-gate Si NW-based FETs decorated with Si NPs show counterclockwise hysteresis loops in the I DS-V GS curves, revealing their significant charge storage effect.",

author = "Jeongmin Kang and Kihyun Keem and Jeong, {Dong Young} and Miyoung Park and Dongmok Whang and Sangsig Kim",

note = "Funding Information: Acknowledgement This work was supported by the Center for Integrated-Nano-Systems (CINS) of the Korea Research Foundation (KRF-2006-005-J03601), the Korea Science and Engineering Foundation (KOSEF) through the National Research Lab. Program (R0A-2005-000-10045-02 (2007)), the Nano R&D Program (M10703000980-07M0300-98010), and {\textquoteleft}{\textquoteleft}SystemIC2010{\textquoteright}{\textquoteright} project of Korea Ministry of Commerce, Industry and Energy.",

year = "2008",

month = may,

doi = "10.1007/s10853-007-2310-6",

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T1 - Electrical characteristics of Si-nanoparticle/Si-nanowire-based field-effect transistors

AU - Kang, Jeongmin

AU - Keem, Kihyun

AU - Jeong, Dong Young

AU - Park, Miyoung

AU - Whang, Dongmok

AU - Kim, Sangsig

N1 - Funding Information: Acknowledgement This work was supported by the Center for Integrated-Nano-Systems (CINS) of the Korea Research Foundation (KRF-2006-005-J03601), the Korea Science and Engineering Foundation (KOSEF) through the National Research Lab. Program (R0A-2005-000-10045-02 (2007)), the Nano R&D Program (M10703000980-07M0300-98010), and ‘‘SystemIC2010’’ project of Korea Ministry of Commerce, Industry and Energy.

PY - 2008/5

Y1 - 2008/5

N2 - In this study, Si-nanoparticle(NP)/Si-nanowire(NW)-based field-effect transistors (FETs) with a top-gate geometry were fabricated and characterized. In these FETs, Si NPs were embedded as localized trap sites in Al 2O3 top-gate layers coated on Si NW channels. Drain current versus drain voltage (I DS-V DS) and drain current versus gate voltage (I DS-V GS) were measured for the Si NP/Si NW-based FETs to investigate their electrical and memory characteristics. The Si NW channels were depleted at V GS= 9 V, indicating that the devices functioned as p-type depletion-mode FETs. The top-gate Si NW-based FETs decorated with Si NPs show counterclockwise hysteresis loops in the I DS-V GS curves, revealing their significant charge storage effect.

AB - In this study, Si-nanoparticle(NP)/Si-nanowire(NW)-based field-effect transistors (FETs) with a top-gate geometry were fabricated and characterized. In these FETs, Si NPs were embedded as localized trap sites in Al 2O3 top-gate layers coated on Si NW channels. Drain current versus drain voltage (I DS-V DS) and drain current versus gate voltage (I DS-V GS) were measured for the Si NP/Si NW-based FETs to investigate their electrical and memory characteristics. The Si NW channels were depleted at V GS= 9 V, indicating that the devices functioned as p-type depletion-mode FETs. The top-gate Si NW-based FETs decorated with Si NPs show counterclockwise hysteresis loops in the I DS-V GS curves, revealing their significant charge storage effect.

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Electrical characteristics of Si-nanoparticle/Si-nanowire-based field-effect transistors

Abstract

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ASJC Scopus subject areas

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