We fabricated a metal-insulator-semiconductor (MIS) structure with V 2O5 nanowires on p-type Si substrates that have been pretreated with 3-aminopropyltriethoxysilane (3-APS) for better adsorption of the nanowires by using a quenching method. The V2O5 nanowires synthesized by using the gel/sol method showed semiconductor properties. For the MIS structure, 50 nm of poly-methylmethcrylate (PMMA) was spin coated on the V2O5 nanowires; then, a Au gate was deposited. The electrical properties of this structure were characterized by using a capacitance-voltage (C-V) measurements. The typical C-V hysteresis appeared at room temperature in the samples treated using a piranah solution for 30 s and 45 s then, the voltage gaps Were measured to be about 5 V and 7.5 V, respectively. These electrical properties show the feasibility of using V 2O5 nanowires for a memory device.
|Number of pages||4|
|Journal||Journal of the Korean Physical Society|
|Publication status||Published - 2006 Sept|
- VO (vanadium pentoxide)
ASJC Scopus subject areas
- Physics and Astronomy(all)