Eliminating conditional branches for enhancing instruction level parallelism in VLIW compiler

In VLIW (Very Long Instruction Word) compiler, one of the most important issue is how to handle conditional branches, because control dependences are caused by conditional branches and limit the scope of scheduling. This paper proposes the efficient method of eliminating conditional branches. We use SSA (Static Single Assignment) information for preserving semantics. By using our methods, global scheduling techniques can be processed more efficiently and simply. We utilized φ-functions aggressively, thus computations for code motion are not required. We don't need complex hardware support. Our scheme also makes the performance independent on the result of branch outcomes.