In this paper, we present an energy-efficient architecture of the Canny edge detector for advanced mobile vision applications. Three key techniques for reducing computational complexity of the Canny edge detector are presented. First, by exploiting the rank characteristic of the convolution kernel of Gaussian smoothing and Sobel gradient filters, common computations are identified and shared in the image filter design to reduce the number of additions and multiplications. For the gradient magnitude/direction computation, only three directions of neighboring pixels are considered to reduce computation energy with minor degradation on conformance performance (CP). For the adaptive threshold selections, an interesting observation is that the mean values of gradient magnitudes show small variations depending on the classified block types. Thus, the threshold selection process can be simplified as multiplying the mean value of the local block with predecided constants. The proposed low complexity Canny edge detector has been implemented using both field-programmable gate arrays (FPGAs) and a 65-nm standard-cell library. The FPGA implementation with Xilinx Virtex-V (XC5VSX240T) shows that our edge detector achieves 48% of area and 73% of execution time savings over the conventional architecture without seriously sacrificing the detection performance. The proposed edge detector implemented with 65-nm standard-cell library can easily support real-time ultrahigh definition video data processing (50 frames/s) with the power consumption of 5.48 mW (108.84 μJ).
|Number of pages||10|
|Journal||IEEE Transactions on Circuits and Systems for Video Technology|
|Publication status||Published - 2018 Apr|
Bibliographical noteFunding Information:
Manuscript received June 29, 2015; revised January 4, 2016 and March 30, 2016; accepted July 26, 2016. Date of publication December 14, 2016; date of current version April 4, 2018. This work was supported in part by the National Research Foundation of Korea under Grant 2011-0020128 and Grant 2016R1A2B4015329, in part by the Information Technology Research and Development Program of Korea Evaluation Institute of Industrial Technology under Grant 10052716 [Design technology development of ultralow voltage operating circuit and IP for smart sensor SoC], and in part by the IC Design Education Center. This paper was recommended by Associate Editor M. Mattavelli.
© 2016 IEEE.
- Canny edge detector
- high-throughput digital signal processor
- low-power image processing
ASJC Scopus subject areas
- Media Technology
- Electrical and Electronic Engineering