Energy-efficient skewed static logic design with dual Vt

Chulwoo Kim; Kiwook Kim; Sung Mo Steve Kang

doi:10.1109/ISCAS.2001.922379

Energy-efficient skewed static logic design with dual Vt

Chulwoo Kim, Kiwook Kim, Sung Mo Steve Kang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we describe skewed static logic (S/sup 2/L) with topology-dependent dual Vt which exhibits energy-efficient operation. S/sup 2/L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S/sup 2/L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 /spl mu/m CMOS technology and verified that S/sup 2/L reduces energy/spl times/delay over MS CMOS by 27-50%. Synthesis algorithm for S/sup 2/L developed and the experimental results show S/sup 2/L consumes 23% less power than MS CMOS with minor increase in delay.

Original language	English
Title of host publication	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages	882-885
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2001.922379
Publication status	Published - 2001
Externally published	Yes
Event	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia Duration: 2001 May 6 → 2001 May 9

Publication series

Name	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume	4

Other

Other	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/Territory	Australia
City	Sydney, NSW
Period	01/5/6 → 01/5/9

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2001.922379

Cite this

Kim, C., Kim, K., & Kang, S. M. S. (2001). Energy-efficient skewed static logic design with dual Vt. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (pp. 882-885). Article 922379 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4). https://doi.org/10.1109/ISCAS.2001.922379

Energy-efficient skewed static logic design with dual Vt. / Kim, Chulwoo; Kim, Kiwook; Kang, Sung Mo Steve.
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. 2001. p. 882-885 922379 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, C, Kim, K & Kang, SMS 2001, Energy-efficient skewed static logic design with dual Vt. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings., 922379, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, vol. 4, pp. 882-885, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 01/5/6. https://doi.org/10.1109/ISCAS.2001.922379

@inproceedings{1fc3487b14c0491899ce12ddf730a835,

title = "Energy-efficient skewed static logic design with dual Vt",

abstract = "In this paper, we describe skewed static logic (S/sup 2/L) with topology-dependent dual Vt which exhibits energy-efficient operation. S/sup 2/L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S/sup 2/L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 /spl mu/m CMOS technology and verified that S/sup 2/L reduces energy/spl times/delay over MS CMOS by 27-50%. Synthesis algorithm for S/sup 2/L developed and the experimental results show S/sup 2/L consumes 23% less power than MS CMOS with minor increase in delay.",

author = "Chulwoo Kim and Kiwook Kim and Kang, {Sung Mo Steve}",

year = "2001",

doi = "10.1109/ISCAS.2001.922379",

language = "English",

isbn = "0780366859",

series = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

pages = "882--885",

booktitle = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",

}

TY - GEN

T1 - Energy-efficient skewed static logic design with dual Vt

AU - Kim, Chulwoo

AU - Kim, Kiwook

AU - Kang, Sung Mo Steve

PY - 2001

Y1 - 2001

N2 - In this paper, we describe skewed static logic (S/sup 2/L) with topology-dependent dual Vt which exhibits energy-efficient operation. S/sup 2/L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S/sup 2/L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 /spl mu/m CMOS technology and verified that S/sup 2/L reduces energy/spl times/delay over MS CMOS by 27-50%. Synthesis algorithm for S/sup 2/L developed and the experimental results show S/sup 2/L consumes 23% less power than MS CMOS with minor increase in delay.

AB - In this paper, we describe skewed static logic (S/sup 2/L) with topology-dependent dual Vt which exhibits energy-efficient operation. S/sup 2/L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S/sup 2/L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 /spl mu/m CMOS technology and verified that S/sup 2/L reduces energy/spl times/delay over MS CMOS by 27-50%. Synthesis algorithm for S/sup 2/L developed and the experimental results show S/sup 2/L consumes 23% less power than MS CMOS with minor increase in delay.

UR - http://www.scopus.com/inward/record.url?scp=84888043521&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84888043521&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2001.922379

DO - 10.1109/ISCAS.2001.922379

M3 - Conference contribution

AN - SCOPUS:84888043521

SN - 0780366859

SN - 9780780366855

T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

SP - 882

EP - 885

BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001

Y2 - 6 May 2001 through 9 May 2001

ER -

Energy-efficient skewed static logic design with dual Vt

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