Energy-efficient Skewed Static Logic design with dual VT

C. Kim; K. Kim; S. M. Kang

Energy-efficient Skewed Static Logic design with dual VT

C. Kim^*, K. Kim, S. M. Kang

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

1 Citation (Scopus)

Abstract

In this paper, we describe Skewed Static Logic (S²L) with topology-dependent dual Vt which exhibits energy-efficient operation. S²L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S²L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S²L reduces energy×delay over MS CMOS by 27-50%. Synthesis algorithm for S²L is developed and the experimental results show S²L consumes 23% less power than MS CMOS with minor increase in delay.

Original language	English
Pages (from-to)	IV882-IV885
Journal	Materials Research Society Symposium - Proceedings
Volume	626
Publication status	Published - 2001
Externally published	Yes
Event	Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States Duration: 2000 Apr 24 → 2000 Apr 27

ASJC Scopus subject areas

General Materials Science
Condensed Matter Physics
Mechanics of Materials
Mechanical Engineering

Cite this

@article{6e19cd1b327242b4b07bb3bbc34b23c0,

title = "Energy-efficient Skewed Static Logic design with dual VT",

abstract = "In this paper, we describe Skewed Static Logic (S2L) with topology-dependent dual Vt which exhibits energy-efficient operation. S2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S2L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S2L reduces energy×delay over MS CMOS by 27-50\%. Synthesis algorithm for S2L is developed and the experimental results show S2L consumes 23\% less power than MS CMOS with minor increase in delay.",

author = "C. Kim and K. Kim and Kang, \{S. M.\}",

year = "2001",

language = "English",

volume = "626",

pages = "IV882--IV885",

journal = "Materials Research Society Symposium - Proceedings",

issn = "0272-9172",

publisher = "Materials Research Society",

note = "Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications ; Conference date: 24-04-2000 Through 27-04-2000",

}

TY - JOUR

T1 - Energy-efficient Skewed Static Logic design with dual VT

AU - Kim, C.

AU - Kim, K.

AU - Kang, S. M.

PY - 2001

Y1 - 2001

N2 - In this paper, we describe Skewed Static Logic (S2L) with topology-dependent dual Vt which exhibits energy-efficient operation. S2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S2L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S2L reduces energy×delay over MS CMOS by 27-50%. Synthesis algorithm for S2L is developed and the experimental results show S2L consumes 23% less power than MS CMOS with minor increase in delay.

AB - In this paper, we describe Skewed Static Logic (S2L) with topology-dependent dual Vt which exhibits energy-efficient operation. S2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S2L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S2L reduces energy×delay over MS CMOS by 27-50%. Synthesis algorithm for S2L is developed and the experimental results show S2L consumes 23% less power than MS CMOS with minor increase in delay.

UR - https://www.scopus.com/pages/publications/0035030902

M3 - Conference article

AN - SCOPUS:0035030902

SN - 0272-9172

VL - 626

SP - IV882-IV885

JO - Materials Research Society Symposium - Proceedings

JF - Materials Research Society Symposium - Proceedings

T2 - Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications

Y2 - 24 April 2000 through 27 April 2000

ER -

Energy-efficient Skewed Static Logic design with dual VT

Abstract

ASJC Scopus subject areas

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