Energy-efficient skewed static logic with dual Vt: Design and synthesis

Chulwoo Kim; Ki Wook Kim; Sung Mo Kang

doi:10.1109/TVLSI.2002.800528

Energy-efficient skewed static logic with dual Vt: Design and synthesis

Chulwoo Kim, Ki Wook Kim, Sung Mo Kang

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

In this paper, we describe skewed static logic (S² L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S² L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S² L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-μm CMOS technology and verified that S² L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S² L with dual Vt reduces delay by 43% and energy-delay product by 31% for 1-V power supply over conventional CMOS circuit. Synthesis algorithm for S² L is developed and the experimental results show S² L consumes 23% less power than MS CMOS with minor increase in delay.

Original language	English
Pages (from-to)	64-70
Number of pages	7
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	11
Issue number	1
DOIs	https://doi.org/10.1109/TVLSI.2002.800528
Publication status	Published - 2003 Feb

Keywords

Accelerator
Adder
Dual Vt
Low power
Skewed logic
Synthesis algorithm

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2002.800528

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title = "Energy-efficient skewed static logic with dual Vt: Design and synthesis",

abstract = "In this paper, we describe skewed static logic (S2 L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S2 L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S2 L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-μm CMOS technology and verified that S2 L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S2 L with dual Vt reduces delay by 43% and energy-delay product by 31% for 1-V power supply over conventional CMOS circuit. Synthesis algorithm for S2 L is developed and the experimental results show S2 L consumes 23% less power than MS CMOS with minor increase in delay.",

keywords = "Accelerator, Adder, Dual Vt, Low power, Skewed logic, Synthesis algorithm",

author = "Chulwoo Kim and Kim, {Ki Wook} and Kang, {Sung Mo}",

note = "Funding Information: Manuscript received January 3, 2001; revised January 16, 2002. This work was supported in part by Semiconductor Research Corporation under SRC Contract 98-HJ-641.",

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doi = "10.1109/TVLSI.2002.800528",

language = "English",

volume = "11",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - Energy-efficient skewed static logic with dual Vt

T2 - Design and synthesis

AU - Kim, Chulwoo

AU - Kim, Ki Wook

AU - Kang, Sung Mo

N1 - Funding Information: Manuscript received January 3, 2001; revised January 16, 2002. This work was supported in part by Semiconductor Research Corporation under SRC Contract 98-HJ-641.

PY - 2003/2

Y1 - 2003/2

N2 - In this paper, we describe skewed static logic (S2 L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S2 L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S2 L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-μm CMOS technology and verified that S2 L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S2 L with dual Vt reduces delay by 43% and energy-delay product by 31% for 1-V power supply over conventional CMOS circuit. Synthesis algorithm for S2 L is developed and the experimental results show S2 L consumes 23% less power than MS CMOS with minor increase in delay.

AB - In this paper, we describe skewed static logic (S2 L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S2 L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S2 L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-μm CMOS technology and verified that S2 L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S2 L with dual Vt reduces delay by 43% and energy-delay product by 31% for 1-V power supply over conventional CMOS circuit. Synthesis algorithm for S2 L is developed and the experimental results show S2 L consumes 23% less power than MS CMOS with minor increase in delay.

KW - Accelerator

KW - Adder

KW - Dual Vt

KW - Low power

KW - Skewed logic

KW - Synthesis algorithm

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JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Energy-efficient skewed static logic with dual Vt: Design and synthesis

Abstract

Keywords

ASJC Scopus subject areas

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