Abstract
In this paper, we present energy-efficient soft error-tolerant techniques for digital signal processing (DSP) systems. The proposed technique, referred to as algorithmic soft error-tolerance (ASET), employs low-complexity estimators of a main DSP block to achieve reliable operation in the presence of soft errors. Three distinct ASET techniques-spatial, temporal and spatio-temporal-are presented. For frequency selective finite-impulse response (FIR) filtering, it is shown that the proposed techniques provide robustness in the presence of soft error rates of up to P er = 10 -2 and P er = 10 -3 in a single-event upset scenario. The power dissipation of the proposed techniques ranges from 1.1 X to 1.7 X (spatial ASET) and 1.05 X to 1.17 X (spatio-temporal and temporal ASET) when the desired signal-to-noise ratio SNR des = 25 dB. In comparison, the power dissipation of the commonly employed triple modular redundancy technique is 2.9 X.
Original language | English |
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Article number | 1637464 |
Pages (from-to) | 336-348 |
Number of pages | 13 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 14 |
Issue number | 4 |
DOIs | |
Publication status | Published - 2006 Apr |
Bibliographical note
Funding Information:Manuscript received January 17, 2005; revised September 28, 2005. This work was supported in part by the Microelectronics Advanced Research Corporation (MARCO) sponsored by the Gigascale System Research Center and in part by the National Science Foundation under Grant CCR 99-79381 and Grant CCR 00-85929.
Keywords
- Digital signal processing (DSP)
- Low-power
- Reduced precision redundancy (RPR)
- Reliability
- Soft error tolerance
- Triple modular redundancy (TMR)
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering