Digital processing-in-memory (PIM) design has been actively researched since it does not need analog-to-digital converters (ADCs) that incur large area and energy consumption. However, due to the limited data flow of digital PIM, the data movement between memory cells still incurs significant energy consumption. In this paper, we propose an energy efficient spin-transfer torque (STT)-MRAM based digital PIM architecture, which can support the computations between different memory cells in column-wise and row-wise. The column-wise directional computation is enabled by employing current summation, and it can diversify the data flow of digital PIM, thus efficiently reducing the number of data movement between memory cells. The simulations with 28nm CMOS process show that the proposed digital PIM architecture achieves the energy saving of 43.7% compared to the state-of art architecture.
|Title of host publication||Proceedings - International SoC Design Conference 2022, ISOCC 2022|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2022|
|Event||19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of|
Duration: 2022 Oct 19 → 2022 Oct 22
|Name||Proceedings - International SoC Design Conference 2022, ISOCC 2022|
|Conference||19th International System-on-Chip Design Conference, ISOCC 2022|
|Country/Territory||Korea, Republic of|
|Period||22/10/19 → 22/10/22|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work was supported by National R&D Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT (NRF-2020M3F3A2A01082591). The EDA tool was supported by the IC Design Education Center(IDEC), Korea.
© 2022 IEEE.
- digital PIM
- spin-transfer torque mram(STT-MRAM)
ASJC Scopus subject areas
- Artificial Intelligence
- Computer Science Applications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality