Energy-efficient three-terminal SiO_x memristor crossbar array enabled by vertical Si/graphene heterojunction barristor

A three-terminal memristor is an electronic memory architecture that is particularly suitable for next-generation devices owing to its customizable intrinsic switching characteristics. However, its slow switching speed and lack of high-density array structure has hindered its applicability thus far. In this study, we have designed and fabricated a novel architecture by vertically integrating a silicon oxide (SiO_x) memristor and a graphene barristor, which can be readily extended to a 16 × 16 crossbar array. Notably, the unipolar resistive switching of the SiO_x memristor can be actively modulated by controlling a silicon (Si) phase filament via the barristor's electrostatic gating. Such gate-tunable SiO_x memristor in the array was observed to exhibit excellent electrical performance, e.g., increased switching speed (up to ~35 ns), increased switching probability, enhanced uniformity, and decreased operating voltage. The energy consumption is also significantly improved 4 nJ to 2 pJ via the gating, which exhibits lower than other three-terminal memristors. Moreover, it was able to sustain a high ON–OFF ratio (>10⁶), multi-bit capability (~9 states), and stable endurance and retention properties regardless of gating. As an additional potential application, nonvolatile universal logic gates, including NOT, NOR, and NAND gates, were successfully implemented in this study based on simple circuits containing gate-tunable SiO_x memristors. We believe that the proposed gate-tunable SiO_x memristor represents a distinctive and novel development toward a fast, low energy, and extendable three-terminal memristor platform for electronic devices, thus undertaking a major step in unleashing the potential of memristors to support the growing demands of cutting-edge technologies.