Enhancement of DRAM Performance by Adopting Metal-Interlayer-Semiconductor Source/Drain Contact Structure on DRAM Cell

Muyeong Son, Seung Geun Jung, Seung Hwan Kim, Euyjin Park, Sul Hwan Lee, Hyun Yong Yu

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


The effects of a metal-interlayer-semiconductor (MIS) source/drain (S/D) contact structure on a dynamic random access memory (DRAM) cell transistor are investigated using 3-D technology computer-aided design simulation. When the MIS S/D contact structure is used in a DRAM cell, the retention time increases by approximately 16.22 times when compared with that of the device using the metal-semiconductor (MS) S/D contact structure owing to the lowered S/D doping concentration, leading to a decrement of the gate-induced drain leakage. Furthermore, the write time and charge-sharing time, respectively, are approximately 0.74 and 0.69 times shorter when compared with the device using the MS S/D contact structure owing to better ohmic characteristics, which increase the drain current during the write/read operations. Thus, the MIS S/D contact structure can effectively enhance the retention and write/read characteristics of a DRAM cell, and it can be a promising S/D contact alternative for the DRAM cell in the sub-2y-nm technology node.

Original languageEnglish
Article number9384164
Pages (from-to)2275-2280
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number5
Publication statusPublished - 2021 May

Bibliographical note

Funding Information:
Manuscript received January 25, 2021; accepted March 10, 2021. Date of publication March 23, 2021; date of current version April 22, 2021. This work was supported in part by the Basic Science Research Program within the Ministry of Science, Information and Communications Technology (ICT), and Future Planning through the National Research Foundation of Korea under Grant 2020R1A2C2004029, in part by SK Hynix Inc., in part by the Korea the Ministry of Trade, Industry & Energy (MOTIE) under Project 20003551, and in part by the Korea Semiconductor Research Consortium (KSRC) Support Program for the development of the future semiconductor device. The review of this article was arranged by Editor P. Narayanan. (Muyeong Son and Seung Geun Jung contributed equally to this work.) (Corresponding author: Hyun-Yong Yu.) Muyeong Son is with the Department of Semiconductor Systems Engineering, Korea University, Seoul 02841, South Korea.

Publisher Copyright:
© 1963-2012 IEEE.


  • 3-D technology computer aided design (TCAD) simulation
  • charge-sharing time
  • contact resistance
  • dynamic random access memory (DRAM)
  • gate-induced drain leakage (GIDL)
  • metal-interlayer-semiconductor (MIS)
  • retention time
  • write time

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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