Exploiting narrow-width values for process variation-tolerant 3-D microprocessors

Joonho Kong, Sung Woo Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)


Process variation is a challenging problem in 3D microprocessors, since it adversely affects performance, power, and reliability of 3D microprocessors, which in turn results in yield losses. In this paper, we propose a novel architectural scheme that exploits the narrow-width value for yield improvement of last-level caches in 3D microprocessors. In a energy-/performance-efficient manner, our proposed scheme improves cache yield by 58.7% and 17.3% compared to the baseline and the naïve way-reduction scheme (that simply discards faulty cache lines), respectively.

Original languageEnglish
Title of host publicationProceedings of the 49th Annual Design Automation Conference, DAC '12
Number of pages10
Publication statusPublished - 2012
Event49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States
Duration: 2012 Jun 32012 Jun 7

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Other49th Annual Design Automation Conference, DAC '12
Country/TerritoryUnited States
CitySan Francisco, CA


  • 3D microprocessor
  • last-level cache
  • narrow-width value
  • process variation
  • yield

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation


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