Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency

Cong Thuan Do; Young Ho Gong; Cheol Hong Kim; Seon Wook Kim; Sung Woo Chung

doi:10.1109/ISLPED.2019.8824947

Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency

Cong Thuan Do, Young Ho Gong, Cheol Hong Kim, Seon Wook Kim, Sung Woo Chung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

The warp scheduler plays an important role in the GPU for efficient utilization of hardware resources. However, the efficiency of the warp scheduler is often limited by the L1 cache (especially, L1 data cache) capacity; providing large capacity for an L1 cache is challenging due to the increased latency. In this paper, we adopt Monolithic 3D (M3D) technology to design a large capacity L1 cache for GPU performance enhancement, not deteriorating the latency. Our evaluation results show that the M3D L1 cache improves GPU performance by 2.18~2.24× on average, compared to the 2D conventional L1 cache.

Original language	English
Title of host publication	International Symposium on Low Power Electronics and Design, ISLPED 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728129549
DOIs	https://doi.org/10.1109/ISLPED.2019.8824947
Publication status	Published - 2019 Jul
Event	2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019 - Lausanne, Switzerland Duration: 2019 Jul 29 → 2019 Jul 31

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
Volume	2019-July
ISSN (Print)	1533-4678

Conference

Conference	2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019
Country/Territory	Switzerland
City	Lausanne
Period	19/7/29 → 19/7/31

Bibliographical note

Funding Information:
Development Program through the National Research Foundation of Korea funded by the Ministry of Science, ICT & Future Planning (MSIP) (No. 2015M3A7B7045470), and Samsung Electronics. We would also like to thank Ji Heon Lee for his help with thermal simulation and anonymous reviewers for their helpful feedback.

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2017R1A2B2002930), Nano Material Technology Development Program through the National Research Foundation of Korea funded by the Ministry of Science, ICT & Future Planning (MSIP) (No. 2015M3A7B7045470), and Samsung Electronics. We would also like to thank Ji Heon Lee for his help with thermal simulation and anonymous reviewers for their helpful feedback.

Funding Information:
ACKNOWLEDGMENT Sung Woo Chung is the corresponding author of this paper. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2017R1A2B2002930), Nano Material Technology

Publisher Copyright:
© 2019 IEEE.

Keywords

GPGPU
Monolithic 3D
Warp Scheduling

ASJC Scopus subject areas

General Engineering

Access to Document

10.1109/ISLPED.2019.8824947

Cite this

Do, C. T., Gong, Y. H., Kim, C. H., Kim, S. W., & Chung, S. W. (2019). Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency. In International Symposium on Low Power Electronics and Design, ISLPED 2019 Article 8824947 (Proceedings of the International Symposium on Low Power Electronics and Design; Vol. 2019-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISLPED.2019.8824947

Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency. / Do, Cong Thuan; Gong, Young Ho; Kim, Cheol Hong et al.
International Symposium on Low Power Electronics and Design, ISLPED 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8824947 (Proceedings of the International Symposium on Low Power Electronics and Design; Vol. 2019-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Do, CT, Gong, YH, Kim, CH, Kim, SW & Chung, SW 2019, Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency. in International Symposium on Low Power Electronics and Design, ISLPED 2019., 8824947, Proceedings of the International Symposium on Low Power Electronics and Design, vol. 2019-July, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019, Lausanne, Switzerland, 19/7/29. https://doi.org/10.1109/ISLPED.2019.8824947

Do CT, Gong YH, Kim CH, Kim SW , Chung SW. Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency. In International Symposium on Low Power Electronics and Design, ISLPED 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8824947. (Proceedings of the International Symposium on Low Power Electronics and Design). doi: 10.1109/ISLPED.2019.8824947

Do, Cong Thuan ; Gong, Young Ho ; Kim, Cheol Hong et al. / Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency. International Symposium on Low Power Electronics and Design, ISLPED 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings of the International Symposium on Low Power Electronics and Design).

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note = "Funding Information: Development Program through the National Research Foundation of Korea funded by the Ministry of Science, ICT & Future Planning (MSIP) (No. 2015M3A7B7045470), and Samsung Electronics. We would also like to thank Ji Heon Lee for his help with thermal simulation and anonymous reviewers for their helpful feedback. Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2017R1A2B2002930), Nano Material Technology Development Program through the National Research Foundation of Korea funded by the Ministry of Science, ICT & Future Planning (MSIP) (No. 2015M3A7B7045470), and Samsung Electronics. We would also like to thank Ji Heon Lee for his help with thermal simulation and anonymous reviewers for their helpful feedback. Funding Information: ACKNOWLEDGMENT Sung Woo Chung is the corresponding author of this paper. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2017R1A2B2002930), Nano Material Technology Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019 ; Conference date: 29-07-2019 Through 31-07-2019",

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Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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