TY - JOUR
T1 - Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling
AU - Chang, I. J.
AU - Park, J.
AU - Kang, K.
AU - Roy, K.
PY - 2010/11
Y1 - 2010/11
N2 - Owing to increase in parametric variations with technology scaling, accurate estimation of bit-cell failure probability in nano-scale static random access memory (SRAM) has become an extremely challenging task. In this study, the authors propose a method to detect the SRAM bit-cell failure, named 'critical point sampling'. Using this technique, read and hold failure probability of an SRAM bit-cell can be efficiently estimated in a simulation-based way. Simulation results show that our estimation method provides high accuracy, while being ∼50× faster in computational speed compared to transient Monte-Carlo simulation. The method can be applied to optimise SRAM design for better yield and contributes significantly in reducing the overall design time.
AB - Owing to increase in parametric variations with technology scaling, accurate estimation of bit-cell failure probability in nano-scale static random access memory (SRAM) has become an extremely challenging task. In this study, the authors propose a method to detect the SRAM bit-cell failure, named 'critical point sampling'. Using this technique, read and hold failure probability of an SRAM bit-cell can be efficiently estimated in a simulation-based way. Simulation results show that our estimation method provides high accuracy, while being ∼50× faster in computational speed compared to transient Monte-Carlo simulation. The method can be applied to optimise SRAM design for better yield and contributes significantly in reducing the overall design time.
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U2 - 10.1049/iet-cds.2010.0137
DO - 10.1049/iet-cds.2010.0137
M3 - Article
AN - SCOPUS:78149374043
SN - 1751-858X
VL - 4
SP - 469
EP - 478
JO - IET Circuits, Devices and Systems
JF - IET Circuits, Devices and Systems
IS - 6
ER -